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公开(公告)号：US08144518B2
公开(公告)日：2012-03-27
申请号：US13099720
申请日：2011-05-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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公开(公告)号：US07646642B2
公开(公告)日：2010-01-12
申请号：US11869144
申请日：2007-10-09
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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3.发明授权公开(公告)号：US07286416B2
公开(公告)日：2007-10-23
申请号：US11194777
申请日：2005-08-02
IPC分类号： G11C7/10
摘要： For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.
摘要翻译： 对于每个存储器块，用于对应用的地址信号进行预编码的预解码器，用于锁存预解码器的输出信号的地址锁存电路和用于解码地址锁存电路的输出信号的解码电路，并且执行存储器单元选择操作 提供相应的存储块。 可以使锁存器预解码信号的传播延迟更小，并且可以扩大内部读取定时的余量。 此外，当选择存储单元并且根据内部数据读取的状态将内部数据输出电路复位到初始状态时，解码器和存储单元选择电路的内部状态处于初始状态。 因此，提供了可以减少地址偏移并实现具有足够余量的操作的非易失性半导体存储器件。
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4.发明申请公开(公告)号：US20060034142A1
公开(公告)日：2006-02-16
申请号：US11194777
申请日：2005-08-02
IPC分类号： G11C8/00
摘要： For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.
摘要翻译： 对于每个存储器块，用于对应用的地址信号进行预编码的预解码器，用于锁存预解码器的输出信号的地址锁存电路和用于解码地址锁存电路的输出信号的解码电路，并且执行存储器单元选择操作 提供相应的存储块。 可以使锁存器预解码信号的传播延迟更小，并且可以扩大内部读取定时的余量。 此外，当选择存储单元并且根据内部数据读取的状态将内部数据输出电路复位到初始状态时，解码器和存储单元选择电路的内部状态处于初始状态。 因此，提供了可以减少地址偏移并实现具有足够余量的操作的非易失性半导体存储器件。
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公开(公告)号：US20110208904A1
公开(公告)日：2011-08-25
申请号：US13099720
申请日：2011-05-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G06F12/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞格的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并且具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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6.发明授权公开(公告)号：US07672173B2
公开(公告)日：2010-03-02
申请号：US11902232
申请日：2007-09-20
IPC分类号： G11C7/00
摘要： For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are reset to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.
摘要翻译： 对于每个存储器块，用于对应用的地址信号进行预编码的预解码器，用于锁存预解码器的输出信号的地址锁存电路和用于解码地址锁存电路的输出信号的解码电路，并且执行存储器单元选择操作 提供相应的存储块。 可以使锁存器预解码信号的传播延迟更小，并且可以扩大内部读取定时的余量。 此外，当选择存储单元并且根据内部数据读取的状态将内部数据输出电路复位到初始状态时，解码器和存储单元选择电路的内部状态被复位到初始状态。 因此，提供了可以减少地址偏移并实现具有足够余量的操作的非易失性半导体存储器件。
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公开(公告)号：US20100080058A1
公开(公告)日：2010-04-01
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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公开(公告)号：US20080089146A1
公开(公告)日：2008-04-17
申请号：US11869144
申请日：2007-10-09
申请人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞格的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并且具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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9.发明申请公开(公告)号：US20080019195A1
公开(公告)日：2008-01-24
申请号：US11902232
申请日：2007-09-20
摘要： For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.
摘要翻译： 对于每个存储器块，用于对应用的地址信号进行预编码的预解码器，用于锁存预解码器的输出信号的地址锁存电路和用于解码地址锁存电路的输出信号的解码电路，并且执行存储器单元选择操作 提供相应的存储块。 可以使锁存器预解码信号的传播延迟更小，并且可以扩大内部读取定时的余量。 此外，当选择存储单元并且根据内部数据读取的状态将内部数据输出电路复位到初始状态时，解码器和存储单元选择电路的内部状态处于初始状态。 因此，提供了可以减少地址偏移并实现具有足够余量的操作的非易失性半导体存储器件。
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公开(公告)号：US07957195B2
公开(公告)日：2011-06-07
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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