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    OPTICAL MEMORY EXTENSION ARCHITECTURE
    2.
    发明申请
    OPTICAL MEMORY EXTENSION ARCHITECTURE 审中-公开
    光学存储器扩展架构

    公开(公告)号：US20140281071A1

    公开(公告)日：2014-09-18

    申请号：US13844083

    申请日：2013-03-15

    申请人： JIANPING JANE XU ,  DONALD FAW ,  VENKATRAMAN IYER

    发明人： JIANPING JANE XU ,  DONALD FAW ,  VENKATRAMAN IYER

    IPC分类号： G06F13/42

    CPC分类号： G06F13/42 ,  G06F13/4045

    摘要： An optical memory extension architecture. A first electrical logic circuit on a first die communicates data according to a packetized, point-to-point interconnect protocol at a full data rate. A first gasket circuit is coupled to receive the data from the first electrical logic circuit. The first gasket circuit causes the data to be converted to an optical format to be transmitted at a rate that is at least double the full data rate. A second gasket circuit is coupled to receive the data in the optical format from the first gasket circuit. The second gasket circuit causes the data to be converted to an electrical format conforming to the packetized, point-to-point interconnect protocol. A second electrical logic circuit on a second die is coupled to receive the data from the first electrical logic circuit through the first gasket circuit and the second gasket circuit.

    摘要翻译： 光学存储器扩展架构。 第一芯片上的第一电逻辑电路以全数据速率根据打包的点对点互连协议传送数据。 第一垫片电路被耦合以从第一电逻辑电路接收数据。 第一垫片电路使得数据被转换成以至少是全数据速率的两倍的速率传输的光学格式。 第二垫片电路被耦合以从第一垫片电路接收光学格式的数据。 第二垫片电路使得数据被转换成符合分组化的点对点互连协议的电格式。 第二管芯上的第二电逻辑电路被耦合以通过第一衬垫电路和第二衬垫电路从第一电逻辑电路接收数据。

    METHOD AND SYSTEM OF REDUCING POWER SUPPLY NOISE DURING TRAINING OF HIGH SPEED COMMUNICATION LINKS
    5.
    发明申请
    METHOD AND SYSTEM OF REDUCING POWER SUPPLY NOISE DURING TRAINING OF HIGH SPEED COMMUNICATION LINKS 审中-公开
    在高速通信链路训练期间减少电源噪声的方法和系统

    公开(公告)号：US20130279622A1

    公开(公告)日：2013-10-24

    申请号：US13976680

    申请日：2011-09-30

    申请人： Venkatraman Iyer ,  Santanu Chaudhuri ,  Stephen S. Chang

    发明人： Venkatraman Iyer ,  Santanu Chaudhuri ,  Stephen S. Chang

    IPC分类号： H04L1/00

    CPC分类号： H04L1/0009 ,  G06F1/10 ,  G06F13/4221 ,  H04L25/03866 ,  H04L25/14 ,  Y02D10/14 ,  Y02D10/151

    摘要： A method and system to reduce the power supply noise of a platform during the training of high speed communication links. In one embodiment of the invention, the device has logic to stagger a bit lock pattern for each of one or more communication links and scramble a training sequence for each of the one or more communication links. By doing so, it removes the need for anti-noise circuits and in turn, reduces the silicon area and power of the devices. Further, by having the logic in the physical layers to facilitate the training of the communication links, it eliminates the need to redesign the package of the devices to shift the resonant frequencies.

    摘要翻译： 一种在高速通信链路训练期间减少平台电源噪声的方法和系统。 在本发明的一个实施例中，该装置具有逻辑以错开针对一个或多个通信链路中的每一个的位锁定模式，并且对于一个或多个通信链路中的每个通信链路加扰训练序列。 通过这样做，它消除了对抗噪声电路的需要，进而降低了器件的硅面积和功率。 此外，通过使物理层中的逻辑有助于通信链路的训练，它消除了重新设计设备的封装以移动谐振频率的需要。

    Method and apparatus for high speed signaling
    6.
    发明授权
    Method and apparatus for high speed signaling 失效
    高速信号传输的方法和装置

    公开(公告)号：US06359951B1

    公开(公告)日：2002-03-19

    申请号：US09089923

    申请日：1998-06-03

    申请人： Jeffrey C. Morriss ,  Venkatraman Iyer

    发明人： Jeffrey C. Morriss ,  Venkatraman Iyer

    IPC分类号： H01L2300

    CPC分类号： G06F13/385

    摘要： Briefly, in accordance with one embodiment of the invention, a method of performing high speed signaling includes the following. A preamble signal and an end of packet (EOP) signal are transmitted at a low frequency using rail-to-rail voltage signal levels. Later, high frequency signaling is transmitted using a voltage signal level swing that is less than rail-to-rail.

    摘要翻译： 简而言之，根据本发明的一个实施例，执行高速信令的方法包括以下。 使用轨至轨电压信号电平以低频率发送前导信号和分组结束（EOP）信号。 之后，使用小于轨到轨的电压信号电平摆幅来传输高频信号。

    Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs
    7.
    发明授权
    Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs 失效
    改进的指针FIFO控制器，用于通过控制RAM的地址输入将标准RAM转换为模拟双FIFO

    公开(公告)号：US4949301A

    公开(公告)日：1990-08-14

    申请号：US836936

    申请日：1986-03-06

    申请人： Sunil P. Joshi ,  Venkatraman Iyer

    发明人： Sunil P. Joshi ,  Venkatraman Iyer

    IPC分类号： G11C7/00 ,  G06F3/06 ,  G06F5/06 ,  G06F5/10 ,  G06F12/06 ,  G06F13/00 ,  G06F13/38 ,  H04L29/02

    CPC分类号： G06F5/065 ,  G06F2205/064 ,  G06F2205/066

    摘要： A RAM buffer controller for managing the address input lines of a RAM buffer to simulate the operation of two FIFO's therein. Apparatus is included for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage "transmit and receive" FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Apparatus is also included for transmitting packets from said buffer organized into one or two linked lists. Further, apparatus is included for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor. Further, apparatus and a method are utilized for recording status and length information at the end of a packet instead of in front thereof and for allowing any incoming packet to be flushed without saving status information or to be flushed while saving its status information.

    摘要翻译： RAM缓冲器控制器，用于管理RAM缓冲器的地址输入线以模拟其中的两个FIFO的操作。 包括用于允许由局部区域网络节点中的节点处理器使用RAM缓冲器控制器随机访问装置来管理“发送和接收”FIFO以对缓冲器的地址空间中的任何地址进行随机访问，而不限制于FIFO边界。 还包括用于将分组从所述缓冲器传送到一个或两个链表中的装置。 此外，包括用于允许RAM缓冲器控制器中当前未选择的任何指针的独立初始化并且用于允许由节点处理器进行读取或写入访问的软件请求的装置。 此外，装置和方法被用于在分组结束而不是在其前面记录状态和长度信息，并且允许任何进入的分组被刷新而不保存状态信息或在保存其状态信息的同时刷新。

    Processor to peripheral interface for asynchronous or synchronous applications
    8.
    发明授权
    Processor to peripheral interface for asynchronous or synchronous applications 失效
    处理器用于异步或同步应用的外设接口

    公开(公告)号：US4785469A

    公开(公告)日：1988-11-15

    申请号：US13845

    申请日：1987-02-12

    申请人： Sunil Joshi ,  Venkatraman Iyer

    发明人： Sunil Joshi ,  Venkatraman Iyer

    IPC分类号： G06F13/12 ,  G06F13/42 ,  H04L29/06 ,  H04L7/02

    CPC分类号： G06F13/4221

    摘要： There is disclosed herein an interface for a peripheral to allow the peripheral to communicate with either synchronous or asynchronous systems. The interface includes a series of flip-flops coupled in a chain to take the combined data strobe and chip select signals from an asynchronous system such as a microprocessor and synchronize the combined signal with the peripheral clock and convert the signal to a pulse. This pulse then emulates the instruction enable pulse received from synchronous microprogrammed systems. If the peripheral is operating in a synchronous sytem, the instruction enable signal from the system is gated through a multiplexer controlled by a mode signal which indicates which mode is active so as to act as the peripheral instruction enable signal. An AND gate gates one bit of the instruction bus with the ANDed chip select and data strobe signals to create a read/write control signal for internal use in controlling the data bus drivers.

    CRC calculation machine for separate calculation of checkbits for the header packet and data packet
    9.
    发明授权
    CRC calculation machine for separate calculation of checkbits for the header packet and data packet 失效
    CRC计算机用于单独计算头包和数据包的校验位

    公开(公告)号：US4712215A

    公开(公告)日：1987-12-08

    申请号：US803367

    申请日：1985-12-02

    申请人： Sunil P. Joshi ,  Venkatraman Iyer

    发明人： Sunil P. Joshi ,  Venkatraman Iyer

    IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/09

    CPC分类号： H03M13/091

    摘要： There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus used 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRC calculation. Several different architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be performed on all bytes of a message while excluding some selected number of bits in the first byte is also disclosed.

    摘要翻译： 这里公开了CRC计算电路，其可以在每个字节时钟周期的8位原始输入数据上计算CRC校验位。 计算装置使用8行移位链接，每行的输入耦合到前一行的数据输出。 每个移动链路将其输入位移位到最高有效位的一位位置，并且所选择的移位链路在它们的输入位和输入异或门的输出之间执行异或运算，其异或运算的一个输入位与 校验和寄存器最高有效字节中的位。 字节宽输出总线用于通过在输出周期期间禁用移位链路阵列来访问来自校验和寄存器的最终校验位，使得CRC数据的字节可以通过阵列移位到位，每个字节每字节周期一个字节 时钟。 提供用于将所有逻辑1强制到第一行移位链路的数据输入的预设逻辑，使得可以在CRC计算的第一个时钟周期期间预设该机器。 公开了几种不同的体系结构，用于允许单独计算头部分组上的CRC比特和数据分组，其中数据分组上的CRC比特可以仅针对数据计算，或者数据加上头部的头部和CRC比特。 还公开了允许对消息的所有字节执行CRC计算的逻辑，同时排除第一字节中的某些所选位数。

    Embedded control channel for high speed serial interconnect
    10.
    发明授权
    Embedded control channel for high speed serial interconnect 有权
    用于高速串行互连的嵌入式控制通道

    公开(公告)号：US09229897B2

    公开(公告)日：2016-01-05

    申请号：US13537837

    申请日：2012-06-29

    申请人： Venkatraman Iyer ,  Debendra Das Sharma ,  Robert G. Blankenship ,  Darren S. Jue

    发明人： Venkatraman Iyer ,  Debendra Das Sharma ,  Robert G. Blankenship ,  Darren S. Jue

    IPC分类号： G06F13/40 ,  G06F13/42

    CPC分类号： G06F13/4291

    摘要： Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis. A link state cycle is employed that includes a link control period during which control information is transferred over the interconnect and a link control interval between link control periods during which other links states are implemented, such as for transferring data or operating the link in a low power state. The link state cycles at transmitter and receiver ports are synchronized to account for link transmit latencies, and the timing of link state cycles corresponding to a bidirectional exchange of link control information may be configured to support an overlapping implementation or to facilitate a request/response link control protocol.

    摘要翻译： 用于在具有多个数据通道的高速串行互连中嵌入控制信道的方法和装置。 通过使用在周期性地通过一个或多个数据通道发送的控制信道数据来控制互连的操作方面。 使用链路状态周期，其包括链路控制周期，在该链路控制周期期间控制信息通过互连传送，以及链路控制周期之间的链路控制间隔，在链路控制周期期间实现其他链路状态，例如用于传送数据或以低的速率操作链路 电源状态 在发射机和接收机端口处的链路状态周期被同步以考虑链路发射延迟，并且与链路控制信息的双向交换相对应的链路状态周期的定时可以被配置为支持重叠实现或促进请求/响应链路 控制协议。