公开(公告)号：US20080173569A1

公开(公告)日：2008-07-24

申请号：US11656657

申请日：2007-01-23

申请人： Valoris L. Forsyth

发明人： Valoris L. Forsyth

IPC分类号： B65D85/90

CPC分类号： H01L21/67333

摘要： A stacking tray for electrical components, such as integrated circuit chips, particularly those of the ball grid array (BGA) type is disclosed. The tray is stackable and includes an upper side and a lower side. An array of storage pockets is formed between the upper side of a lower tray and the lower side of an upper tray. The storage pockets are separated by complementary support elements and further include a segmented pedestal arising from the center of the storage pocket, on the upper side of the trays. The segmented pedestal supports the integrated circuit chip, without interfering with the spherical balls. Moreover, the tray allows for variation of the dimensions of the integrated circuit chip while adequately stabilizing the chip.

摘要翻译： 公开了用于诸如集成电路芯片，特别是球栅阵列（BGA）类型的集成电路芯片的电气部件的堆垛盘。 托盘是可堆叠的并且包括上侧和下侧。 在下托盘的上侧和上托盘的下侧之间形成一组储存袋。 存储袋由互补的支撑元件分开，并且还包括在托盘的上侧从存储袋的中心产生的分段底座。 分段底座支撑集成电路芯片，不会干扰球形球。 此外，托盘允许集成电路芯片的尺寸的变化，同时充分稳定芯片。

公开(公告)号：US20080313863A1

公开(公告)日：2008-12-25

申请号：US11820544

申请日：2007-06-20

申请人： Henry Swain ,  Lynnette Dehnke ,  Lawrence Share ,  Valoris L. Forsyth

发明人： Henry Swain ,  Lynnette Dehnke ,  Lawrence Share ,  Valoris L. Forsyth

IPC分类号： A44B19/26 ,  B65D33/16

CPC分类号： A44B19/267 ,  A44B19/32 ,  Y10T24/15 ,  Y10T24/2561 ,  Y10T24/2584 ,  Y10T24/45168

摘要： The water-resistant or waterproof zipper includes first and second profiles which are interlocked or separated by the movement of a slider. The first sidewall of the slider is generally planar while the second sidewall is generally curved so that the sidewalls are relatively closer together at the closing end and generally further apart at the opening end. A triangular island and separating plow are formed at the opening end to separate the first and second profiles. The slider includes various channels which engage corresponding rails in the profiles in order to properly position the profiles. The slider further includes various protrusions and a flange to properly position the profiles.

摘要翻译： 防水或防水拉链包括第一和第二轮廓，其通过滑动件的运动互锁或分离。 滑块的第一侧壁通常是平面的，而第二侧壁通常是弯曲的，使得侧壁在关闭端处相对更靠近在一起，并且在开口端处通常进一步分开。 在开口端形成三角形岛和分离犁以分离第一和第二轮廓。 滑块包括各种通道，其与轮廓中的对应轨道接合，以便正确地定位轮廓。 滑块还包括各种突起和用于使轮廓正确定位的凸缘。

公开(公告)号：USD460688S1

公开(公告)日：2002-07-23

申请号：US29139301

申请日：2001-03-28

申请人： Valoris L. Forsyth

设计人： Valoris L. Forsyth

公开(公告)号：US20110308050A1

公开(公告)日：2011-12-22

申请号：US12967179

申请日：2010-12-14

申请人： Henry SWAIN ,  Lynnette COLBY ,  Lawrence SHARE ,  Valoris L. FORSYTH

发明人： Henry SWAIN ,  Lynnette COLBY ,  Lawrence SHARE ,  Valoris L. FORSYTH

IPC分类号： A44B19/26

CPC分类号： B65D33/2591 ,  A44B19/267 ,  A44B19/32

摘要： The water-resistant zipper includes first and second profiles which are interlocked or separated by the movement of a slider. A triangular island and separating plow are formed at the opening end to separate the first and second profiles. The slider includes various channels which engage corresponding rails in the profiles in order to properly position the profiles.

摘要翻译： 防水拉链包括第一和第二轮廓，其通过滑块的移动而互锁或分开。 在开口端形成三角形岛和分离犁以分离第一和第二轮廓。 滑块包括各种通道，其与轮廓中的对应轨道接合，以便正确地定位轮廓。

公开(公告)号：US20090090653A1

公开(公告)日：2009-04-09

申请号：US11920028

申请日：2004-05-18

申请人： Valoris L Forsyth

发明人： Valoris L Forsyth

IPC分类号： H01L21/673 ,  B65D21/02 ,  B65D81/02 ,  B65D85/30

CPC分类号： H01L21/67369 ,  B65D81/02 ,  B65D85/38

摘要： The wafer box includes a tray (10) and a cover (62). The tray (10) includes an inner (34, 36, 38, 40) and outer (24, 26, 28, 30) wall configuration with horizontal semicircular channels (48, 50, 52, 54) therebetween to perform spacing, strengthening and horizontal shock-absorbing functions. The tray (10) further includes a wafer cavity (42) formed within the inner wall (34, 36, 38, 40). The wafer cavity (42) includes a lattice (46) of ridges on the floor thereof to provide a vertical shock absorbing function. The wall (76, 78, 80, 82) of the cover (62) engages and mates to the outer wall (24, 26, 28, 30) of the tray (10) thereby forming a double wall configuration. A pedestal configuration (90, 92) is formed on the corners and mid-spans of the top of the cover (62) to provide standoff clearance between the inter-stacked boxes to minimize or eliminate the transmission of shock and vibration through an inter-stack configuration.

摘要翻译： 晶片盒包括托盘（10）和盖（62）。 托盘（10）包括在其间具有水平半圆形通道（48,50,52,54）的内部（34,36,38,40）和外部（24,26,28,30）壁构造，以实现间隔，加强和 水平减震功能。 托盘（10）还包括形成在内壁（34,36,38,40）内的晶片空腔（42）。 晶片空腔（42）包括在其底板上的脊格（46），以提供垂直的冲击吸收功能。 盖（62）的壁（76,78,80,82）与托盘（10）的外壁（24,26,28,30）接合并配合，从而形成双壁结构。 在盖（62）的顶部的角部和中间跨度处形成基座构造（90,92），以在堆叠间的箱之间提供间隙，以最小化或消除冲击和振动的传播， 堆栈配置。

公开(公告)号：US07431162B2

公开(公告)日：2008-10-07

申请号：US11182438

申请日：2005-07-15

申请人： Valoris L. Forsyth

发明人： Valoris L. Forsyth

IPC分类号： B65D85/30

CPC分类号： H01L21/67353 ,  H01L21/67369 ,  H01L21/67373 ,  H01L21/67386

摘要： The present disclosure pertains to a wafer box for transporting semiconductor wafers, typically in a coin stack configuration. The wafer box includes an outer box and at least one inner box. The semiconductor wafers are placed in the inner box or boxes, typically with appropriate separators and interleaves. The outer box includes a tray portion and a lid portion. The tray portion includes posts rising from its floor which are received by sleeves in the inner box. Shock absorbing rings are placed on the posts both above and below the inner box or boxes in order to provide protection against vertical shocks. Moreover, the outer box includes radially pivoting latching elements with padded bumper elements. These padded bumper elements are brought to an upright position to urge against the inner box or boxes in order to provide horizontal or lateral shock protection.

摘要翻译： 本公开涉及用于传输半导体晶片的晶片盒，通常以硬币堆叠配置。 晶片盒包括外箱和至少一个内盒。 将半导体晶片放置在内盒或盒中，通常具有合适的分离器和交错。 外箱包括托盘部分和盖部分。 托盘部分包括从其地板上升起的柱，其由内盒中的套筒接收。 冲击吸收环放置在内箱或箱的上方和下方的柱上，以提供防止垂直冲击的保护。 此外，外箱包括具有填充保险杠元件的径向枢转的闩锁元件。 这些填充的保险杠元件被带到直立位置以推动内箱或箱，以便提供水平或横向的冲击保护。

公开(公告)号：US06933033B1

公开(公告)日：2005-08-23

申请号：US10919640

申请日：2004-08-17

申请人： Valoris L. Forsyth ,  Sandrine Charrier

发明人： Valoris L. Forsyth ,  Sandrine Charrier

IPC分类号： B32B3/02 ,  H01L21/00 ,  H01L21/30 ,  H01L21/673

CPC分类号： H01L21/67366 ,  H01L21/67396 ,  Y10T428/21 ,  Y10T428/2457

摘要： A separator of semiconductor wafers is made from polyethylene with a dissipative material and includes a first and second set of embossed cut perpendicular lines. The first set is typically parallel to the second set, and each set includes pairs of cut lines which are spaced from adjacent pairs. The depth of grid lines cut into the material allows air flow, circulation and vacuum release.

摘要翻译： 半导体晶片的分离器由具有耗散材料的聚乙烯制成，并且包括第一组和第二组压花切割的垂直线。 第一组通常平行于第二组，并且每组包括与相邻对间隔的切割线对。 切割成材料的网格线的深度允许空气流动，循环和真空释放。

公开(公告)号：US09048272B2

公开(公告)日：2015-06-02

申请号：US13054104

申请日：2009-09-24

申请人： Valoris L. Forsyth ,  Justin L. Lawrence ,  John E. Vannortwick ,  Jamie J. Wanke ,  Christopher E. Casey ,  Michael R. Forbis ,  James R. Stoor ,  Michael R. Slaughter

发明人： Valoris L. Forsyth ,  Justin L. Lawrence ,  John E. Vannortwick ,  Jamie J. Wanke ,  Christopher E. Casey ,  Michael R. Forbis ,  James R. Stoor ,  Michael R. Slaughter

IPC分类号： B65D85/30 ,  H01L21/673 ,  B29C65/56 ,  B29C45/00 ,  B29C65/00 ,  B29L12/00 ,  B29L31/00

CPC分类号： H01L21/67356 ,  B29C45/0053 ,  B29C65/561 ,  B29C65/562 ,  B29C66/5346 ,  B29L2012/00 ,  B29L2031/737 ,  B65D1/34 ,  B65D25/10 ,  H01L21/67333 ,  H01L21/67369 ,  H01L21/67373

摘要： The disclosure relates to trays for the handling and shipping of computer chips, or similar microelectronic devices. The tray include a series of channels, each extending along a width of the tray. The channels include such devices as pins and clips for securing a thermoformed tape. The thermoformed tape includes pockets for storing the various computer chips, or similar microelectronic devices.

摘要翻译： 本公开涉及用于处理和运送计算机芯片或类似的微电子器件的托盘。 托盘包括一系列通道，每个通道沿托盘的宽度延伸。 通道包括用于固定热成型带的销和夹子的装置。 热成型带包括用于存储各种计算机芯片或类似的微电子器件的口袋。

公开(公告)号：US07565980B2

公开(公告)日：2009-07-28

申请号：US10507471

申请日：2004-05-11

申请人： Valoris L. Forsyth ,  Jim Gardiner ,  Berry Brown

发明人： Valoris L. Forsyth ,  Jim Gardiner ,  Berry Brown

IPC分类号： B65D85/00

CPC分类号： H01L21/67369 ,  H01L21/67373

摘要： The semiconductor wafer containment device or wafer box includes a base with a planar floor and a double concentric cylindrical wall structure arising therefrom. The double concentric cylindrical wall structure includes slots through which latch elements pivot radially. The latch elements include an inward padded spacer element. The latch elements pivot between an outward position wherein the padded spacer elements are relatively away from the wafer containment space and an inward upright position wherein the padded spacer elements impinge into the wafer containment space and are urged against the semiconductor wafers therein. Ramps on the lid capture the latch elements in the outward position and urge the latch elements to pivot to the inward upright position and be detent engaged in this position by slots formed on the lid.

摘要翻译： 半导体晶片封装装置或晶片盒包括具有平面底板和由其产生的双重同心圆柱形壁结构的底座。 双同心圆柱形壁结构包括狭槽，闩锁元件通过该狭槽径向枢转。 闩锁元件包括向内填充的间隔元件。 闩锁元件在外部位置之间枢转，其中填充的间隔元件相对远离晶片容纳空间和向内直立位置，其中填充的间隔元件撞击晶片容纳空间并且被推靠在其中的半导体晶片上。 盖上的斜坡在向外的位置捕获闩锁元件，并且推动闩锁元件枢转到向内直立的位置，并且通过形成在盖上的槽被卡定在该位置。

公开(公告)号：US07225929B2

公开(公告)日：2007-06-05

申请号：US11026101

申请日：2004-12-30

申请人： Valoris L. Forsyth

发明人： Valoris L. Forsyth

IPC分类号： B65D85/48

CPC分类号： H01L21/67346 ,  H01L21/67386

摘要： An adjustable height wafer box for the transportation of coin-stacked semiconductor wafers is disclosed. The adjustable height wafer box comprises a base plate, a cover plate, a plurality of ring insert plates and elastomer bumpers. The ring insert plates are stacked so as to successively engage one another, as well as engaging the base plate and the cover plate. The elastomer bumpers are engaged between successive ring insert plates and extend inwardly into the wafer containment space. The number of ring insert plates can be chosen to adjust the height of the wafer box in accordance with the number of coin-stacked semiconductor wafers to be shipped.

摘要翻译： 公开了用于输送硬币堆叠的半导体晶片的可调高度晶片盒。 可调高度的晶片盒包括基板，盖板，多个环形插入板和弹性体缓冲器。 环形插入板被堆叠以便彼此相继地接合，以及接合基板和盖板。 弹性体缓冲器在连续的环形插入板之间接合并向内延伸进入晶片容纳空间。 可以根据要运输的硬币堆叠的半导体晶片的数量来选择环形插入板的数量来调整晶片盒的高度。