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公开(公告)号：US07450659B2
公开(公告)日：2008-11-11
申请号：US10814472
申请日：2004-03-29
IPC分类号： H04L27/00
CPC分类号： H03C3/40
摘要： An upconverting circuit is disclosed. The upconverting circuit includes a polyphase component generator that provides Np polyphase components at each input polyphase cycle, wherein Np>2 on each input polyphase cycle defined by a clock. A memory stores the polyphase components from at least one polyphase cycle prior to the current polyphase cycle. A plurality of filters process the polyphase components stored in the memory. Each filter processes a plurality of the polyphase components to generate a filtered polyphase component corresponding to that filter. A multiplexer outputs the filtered polyphase components in a predetermined order to generate a filtered output signal. In one embodiment, each filter utilizes the same functional relationship to generate the filtered polyphase components. In another embodiment, the memory is a shift register. The filters can be of arbitrary complexity.
摘要翻译： 公开了一种上变频电路。 上变频电路包括多相分量发生器，其在每个输入多相周期处提供N p个多相分量，其中在由时钟限定的每个输入多相周期上的N p P 2。 存储器存储来自当前多相循环之前的至少一个多相循环的多相成分。 多个滤波器处理存储在存储器中的多相分量。 每个滤波器处理多个多相分量以产生对应于该滤波器的滤波多相分量。 多路复用器以预定顺序输出滤波后的多相分量以产生经滤波的输出信号。 在一个实施例中，每个滤波器利用相同的功能关系来产生滤波的多相分量。 在另一个实施例中，存储器是移位寄存器。 过滤器可以是任意复杂的。
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2.发明授权公开(公告)号：US07148828B2
公开(公告)日：2006-12-12
申请号：US11120698
申请日：2005-05-03
IPC分类号： H03M1/10
CPC分类号： H03M1/10 , H03M1/1205 , H03M1/662
摘要： A method for calibrating time interleaved samplers comprising applying a calibration signal to a time-interleaved sampling device, wherein the signal is coherent with at least one sample clock on the device and is periodic and has a predetermined spectral content and frequency, sampling, by said time-interleaved sampling device, the calibration signal at a plurality of phases to form samples, averaging the formed samples, and calculating the phase error of each sample based on the average calibration signal sample.
摘要翻译： 一种用于校准时间交织采样器的方法，包括将校准信号施加到时间交织的采样设备，其中所述信号与所述设备上的至少一个采样时钟相干，并且是周期性的并且具有预定的频谱含量和频率，由所述 时间交织采样装置，多个相位的校准信号，以形成样本，对所形成的样本进行平均，以及基于平均校准信号样本计算每个样本的相位误差。
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3.发明授权Method and apparatus for clock gating clock trees to reduce power dissipation 有权用于时钟门控时钟树的方法和设备，以减少功耗公开(公告)号：US06822481B1
公开(公告)日：2004-11-23
申请号：US10461531
申请日：2003-06-12
IPC分类号： H03K1900
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： A clock gating circuit reduces the power dissipation in a digital circuit including at least one functional block by gating the clock signal at an input to a clock tree feeding the functional block. The clock gating circuit includes a logic gate that receives a clock signal and a clock disable signal generated by the functional block, and gates the clock signal at the input to the clock tree feeding the functional block. Further, a global signal generator is provided to transmit a global signal to each of the functional blocks to prevent the generation of clock disable signals, when necessary, such as during testing of chips.
摘要翻译： 时钟选通电路通过在馈送功能块的时钟树的输入处门控时钟信号来减少包括至少一个功能块的数字电路中的功率消耗。 时钟选通电路包括接收由功能块产生的时钟信号和时钟禁止信号的逻辑门，并且将馈入功能块的时钟树的输入端的时钟信号进行门控。 此外，提供全局信号发生器以将全局信号发送到每个功能块，以防止在必要时产生时钟禁止信号，例如在芯片测试期间。
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4.发明授权Method and apparatus for defining an input state vector that achieves low power consumption in digital circuit in an idle state 失效用于定义在空闲状态下在数字电路中实现低功耗的输入状态向量的方法和装置公开(公告)号：US07096374B2
公开(公告)日：2006-08-22
申请号：US10443503
申请日：2003-05-21
IPC分类号： G06F1/26
CPC分类号： G06F1/3228 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： The method defines an input state vector that achieves low power consumption when applied to the circuit inputs of a digital circuit in an idle state. The digital circuit includes one or more circuit elements of respective circuit element types. In the method, idle power values including idle power values for each circuit element type. The idle power values for each circuit element type correspond to different states of the inputs of a circuit element of the circuit element type. Additionally the idle power values are used to determine, for each circuit element, states of the inputs of the circuit element that would set the circuit element to a lowest-allowable idle power state when the digital circuit is in the idle state. The states determined for those of the inputs that constitute the circuit inputs define the input state vector. The states are also determined accounting for the logic constraints of the digital circuit.
摘要翻译： 该方法定义了一种输入状态向量，当向空闲状态的数字电路的电路输入端施加时，该状态矢量能实现低功耗。 数字电路包括各个电路元件类型的一个或多个电路元件。 在该方法中，空闲功率值包括每个电路元件类型的空闲功率值。 每个电路元件类型的空闲功率值对应于电路元件类型的电路元件的输入的不同状态。 此外，空闲功率值用于为每个电路元件确定当数字电路处于空闲状态时将电路元件的输入设置为最低允许空闲功率状态的状态。 为构成电路输入的输入端确定的状态定义了输入状态向量。 这些状态也被确定为占用数字电路的逻辑约束。
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5.发明授权Method and apparatus for defining an input state vector that achieves low power consumption in a digital circuit in an idle state 失效用于定义在空闲状态下在数字电路中实现低功耗的输入状态向量的方法和装置公开(公告)号：US07085942B2
公开(公告)日：2006-08-01
申请号：US10443555
申请日：2003-05-21
CPC分类号： G06F1/3203
摘要： The method defines an input state vector that achieves low power consumption when applied to the circuit inputs of a digital circuit in an idle state. In the method, independent determinations are performed. Each determination defines a respective set of the input states of the input state vector. Any conflict the definitions of any one or more of the input states is resolved in favor of the definition of the one or more of the input states that achieves the lowest idle power consumption when the input state vector incorporating the one or more of the input states in accordance with the definition is applied to the circuit inputs of the digital circuit in the idle state.
摘要翻译： 该方法定义了一种输入状态向量，当向空闲状态的数字电路的电路输入端施加时，该状态矢量能实现低功耗。 在该方法中，执行独立的确定。 每个确定定义输入状态向量的相应输入状态集合。 任何冲突，任何一个或多个输入状态的定义被解析为有利于当包含一个或多个输入状态的输入状态向量时实现最低空闲功耗的一个或多个输入状态的定义 按照定义适用于数字电路在空闲状态下的电路输入。
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公开(公告)号：US06601230B2
公开(公告)日：2003-07-29
申请号：US09828321
申请日：2001-04-05
申请人： Vamsi K. Srikantam
发明人： Vamsi K. Srikantam
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A circuit design system that obtains low power circuit design through judicious module selection. The circuit design system implements methods that enable advantageous design tradeoffs between low power behavior and a set of design constraints during module selection. The circuit design system selects unsigned modules which consume less power than signed modules where permitted in view of a desired response of a circuit and where advantageous for low power behavior while not violating the design constraints.
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