-
公开(公告)号：US11538524B2
公开(公告)日：2022-12-27
申请号：US17373118
申请日：2021-07-12
申请人： Weebit Nano Ltd.
发明人： Lior Dagan
摘要： A resistive random-access memory (ReRAM) cell formed on a silicon over insulator substrate (SOI) is provided. The ReRAM includes a SOI substrate, a first MOSFET and a second MOSFET, each of which having a drain port, a gate port, a source port, and a bulk port. The drain port of the second MOSFET is connected to the source port of the first MOSFET; a first resistive element and a second resistive element, each having a first port and a second port, wherein the first ports of both resistive elements are connected to the drain of the first MOSFET; a first word line and a second word line connected to the gate port of the first MOSFET and the second MOSFET, respectively; and the state of the ReRAM cell is determined upon applying a predefined potential.
-
2.发明申请公开(公告)号：US20220336017A1
公开(公告)日：2022-10-20
申请号：US17618250
申请日：2020-06-11
摘要： A method for determining a value of a manufacturing parameter of a resistive memory cell, the resistive memory cell including a stack of layers, includes providing reference memory cells corresponding to technological alternatives of the stack of layers; measuring for each reference memory cell an initial resistance value; determining for each reference memory c ell a programming parameter value selected from among the resistance in a high resistance state and the programming window; establishing a relationship between the programming parameter and the initial resistance from the initial resistance values and the programming parameter values; and determining the manufacturing parameter value for which the programming parameter is greater than or equal to a target value, from the relationship between the programming parameter and the initial resistance and from a dependency relationship between the initial resistance and the manufacturing parameter.
-
公开(公告)号：US20220284955A1
公开(公告)日：2022-09-08
申请号：US17653353
申请日：2022-03-03
申请人： Weebit Nano Ltd.
发明人： Lior DAGAN , Ilan SEVER
IPC分类号： G11C13/00
摘要： A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.
-
公开(公告)号：US12119059B2
公开(公告)日：2024-10-15
申请号：US17990723
申请日：2022-11-20
CPC分类号： G11C13/0069 , G11C13/004 , G11C29/52
摘要： A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.
-
公开(公告)号：US12040017B2
公开(公告)日：2024-07-16
申请号：US17646427
申请日：2021-12-29
申请人： Weebit Nano Ltd.
发明人： Lior Dagan
CPC分类号： G11C13/0069 , H10B63/00 , G11C2013/0071
摘要： A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert.
-
公开(公告)号：US20230170023A1
公开(公告)日：2023-06-01
申请号：US17782446
申请日：2020-12-03
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/004
摘要： A method for resetting an array of Resistive Memory cells by applying a sequence of N reset operations, each reset operation including the application of a reset technique, the method including, at the first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield; at the j-th reset operation of the N−1 subsequent reset operations, j being an integer number between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation.
-
公开(公告)号：US20220392528A1
公开(公告)日：2022-12-08
申请号：US17831948
申请日：2022-06-03
IPC分类号： G11C13/00
摘要： A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.
-
8.发明公开公开(公告)号：US20230162789A1
公开(公告)日：2023-05-25
申请号：US18057000
申请日：2022-11-18
申请人： Weebit Nano Ltd.
发明人： Lior DAGAN
CPC分类号： G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C7/12 , G11C8/08 , G11C2213/53
摘要： A memory including a memory array having a plurality of bit-line inputs and a plurality of word-line inputs; a bit-line decoder; and a control circuit is provided. The bit-line decoder includes a first circuit and a second circuit including a plurality of low-voltage field effect transistors (FET). The control circuit provides control signals to the plurality of low-voltage FETs in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein at the pulse phase, the first circuit and the second circuit receives a desired voltage. The control circuit provide control signals the plurality of low-voltage FETs a voltage no greater than a low-voltage at the pre-pulse phase and the post-pulse phase. In silicon-on-insulator (SOI) technologies, use of low-voltage FETs in the bit-line and word-line decoders reduces the area of the periphery circuits of the memory array without requiring change to the memory array itself.
-
公开(公告)号：US11659720B2
公开(公告)日：2023-05-23
申请号：US17373102
申请日：2021-07-12
申请人： Weebit Nano Ltd.
发明人： Lior Dagan
CPC分类号： H01L27/2436 , G11C13/004 , G11C13/0069 , H01L27/1203 , G11C2213/74 , G11C2213/79
摘要： A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.
-
公开(公告)号：US20230008586A1
公开(公告)日：2023-01-12
申请号：US17782423
申请日：2020-12-01
IPC分类号： G11C13/00
摘要： A method for resetting an array of RAM cells by applying a sequence of N reset operations, the method including at a first reset operation, defining a first reset technique and performing the first reset operation; at a j-th reset operation of a N-1 subsequent reset operations, j being an integer between 2 and N, if a correction yield of the reset technique used at the (j-1)-th reset operation fulfils a predefined condition, applying the reset technique used at the (j-1)-th reset operation to perform the j-th reset operation, if the correction yield does not fulfil the predefined condition, defining a new reset technique and applying the new reset technique to perform the j-th reset operation, the correction yield being a cumulative correction yield or a relative correction yield, the correction yield for the N reset operations being measured prior to the first reset operation.
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.013 秒)
