公开(公告)号：US09053247B2

公开(公告)日：2015-06-09

申请号：US13299160

申请日：2011-11-17

申请人： Wataru Ochiai

发明人： Wataru Ochiai

IPC分类号： G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4059

摘要： By connecting, to a bus bridge according to a configuration of a bus system, a monitor circuit including an activation control circuit generating a counter activation signal from an input monitor activation signal, a counter circuit, activated by the counter activation signal, counting the transfer number using a signal of bridge transfer completion indicating an issuance of one transfer from a bus bridge, and outputting a count completion signal when the transfers of the same number as that stuck in the bus bridge indicated by the signal of the transfer number stuck in the bridge is issued when being activated, and a completion control circuit outputting a monitor completion signal upon receiving the count completion signal from the counter circuit, consistency of data may be guaranteed in any bus system without changing the configuration of the bus bridge based on the number of masters accessing the bus bridge.

摘要翻译： 通过根据总线系统的配置连接到总线桥，监视电路包括激活控制电路，其从输入监视器激活信号产生计数器激活信号，由计数器激活信号激活的计数器电路，计数传送 数字，使用桥接传输完成信号，指示从总线桥发出一次传送，并且当与由传送号码的信号卡住的总线桥中所卡住的相同号码的传输被卡在该传输号码中时，输出计数完成信号 桥接器被激活时发出，并且完成控制电路在从计数器电路接收到计数完成信号时输出监视完成信号，可以在任何总线系统中保证数据的一致性，而不需要改变总线桥的配置 的主人进入公共汽车桥。

公开(公告)号：US20090310670A1

公开(公告)日：2009-12-17

申请号：US12484861

申请日：2009-06-15

申请人： Masayuki Odagawa ,  Wataru Ochiai ,  Akihiro Takamura

发明人： Masayuki Odagawa ,  Wataru Ochiai ,  Akihiro Takamura

IPC分类号： H04N7/12

CPC分类号： H04N7/24 ,  H04N19/176 ,  H04N19/187 ,  H04N19/188 ,  H04N19/196 ,  H04N19/44 ,  H04N19/70

摘要： An information processing system for performing processing of dividing a moving image into tiles and packetizing and outputting information corresponding to each tile includes a process time measuring packet generation unit adapted to generate and transmit a process time measuring packet in which a packet sending time is set to measure a packet process time, a packet process time measuring unit adapted to measure, based on the packet sending time set in the process time measuring packet and the reception time of the process time measuring packet, the packet process time necessary for processing a packet, a determination unit adapted to determine, based on the packet process time, the timestamp of the moving image divided into the tiles, and a packetization unit adapted to execute processing of packetizing and outputting the timestamp and the information of the moving image divided into the tiles.

摘要翻译： 一种用于执行将运动图像划分成瓦片并分组并输出与每个瓦片相对应的信息的处理的信息处理系统，包括：处理时间测量分组生成单元，适于生成并发送分组发送时间设置为 测量分组处理时间，分组处理时间测量单元，基于在处理时间测量分组中设置的分组发送时间和处理时间测量分组的接收时间来测量处理分组所需的分组处理时间， 确定单元，适于基于分组处理时间确定划分为瓦片的运动图像的时间戳;以及分组单元，适用于执行分组和输出时间戳的处理以及划分为瓦片的运动图像的信息 。

公开(公告)号：US08856465B2

公开(公告)日：2014-10-07

申请号：US13225294

申请日：2011-09-02

申请人： Makoto Fujiwara ,  Wataru Ochiai

发明人： Makoto Fujiwara ,  Wataru Ochiai

IPC分类号： G06F12/00 ,  G06F1/32

CPC分类号： G06F1/3225 ,  G06F1/3275 ,  G06F13/1626 ,  Y02D10/13 ,  Y02D10/14

摘要： Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory control apparatus, which is connected with a plurality of masters and a plurality of memories having a power saving mode, arbitrates memory accesses from the plurality of the masters, monitors whether each of the plurality of the memories is in the power saving state, and determines the priorities of the memory accesses according to the result of the detection of the power saving mode.

摘要翻译： 对处于省电模式的存储器件的存储器访问取决于其发布的顺序。 因此，有时缩短存储器处于省电模式的时间段，导致功率节省效果较差。 与多个主器件连接的存储器控​​制装置和具有省电模式的多个存储器来对来自多个主器件的存储器访问进行仲裁，监视多个存储器中的每一个是否处于省电状态， 并且根据省电模式的检测结果确定存储器访问的优先级。

公开(公告)号：US20120137033A1

公开(公告)日：2012-05-31

申请号：US13299160

申请日：2011-11-17

申请人： Wataru Ochiai

发明人： Wataru Ochiai

IPC分类号： G06F13/10

CPC分类号： G06F13/4059

摘要： By connecting, to a bus bridge according to a configuration of a bus system, a monitor circuit including an activation control circuit generating a counter activation signal from an input monitor activation signal, a counter circuit, activated by the counter activation signal, counting the transfer number using a signal of bridge transfer completion indicating an issuance of one transfer from a bus bridge, and outputting a count completion signal when the transfers of the same number as that stuck in the bus bridge indicated by the signal of the transfer number stuck in the bridge is issued when being activated, and a completion control circuit outputting a monitor completion signal upon receiving the count completion signal from the counter circuit, consistency of data may be guaranteed in any bus system without changing the configuration of the bus bridge based on the number of masters accessing the bus bridge.

摘要翻译： 通过根据总线系统的配置连接到总线桥，监视电路包括激活控制电路，其从输入监视器激活信号产生计数器激活信号，由计数器激活信号激活的计数器电路，计数传送 数字，使用桥接传输完成信号，指示从总线桥发出一次传送，并且当与由传送号码的信号卡住的总线桥中所卡住的相同号码的传输被卡在该传输号码中时，输出计数完成信号 桥接器被激活时发出，并且完成控制电路在从计数器电路接收到计数完成信号时输出监视完成信号，可以在任何总线系统中保证数据的一致性，而不需要改变总线桥的配置 的主人进入公共汽车桥。

公开(公告)号：US08169852B2

公开(公告)日：2012-05-01

申请号：US12774266

申请日：2010-05-05

申请人： Wataru Ochiai

发明人： Wataru Ochiai

IPC分类号： G11C8/18

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G06F13/1668 ,  Y02D10/13 ,  Y02D10/14

摘要： A circuit configured to change a mode of a plurality of memory devices having a power saving mode includes a command queue configured to hold memory access, and a cancellation unit configured to cancel the power saving mode of target devices of the memory access held up to a predetermined stage of the command queue.

摘要翻译： 配置为改变具有省电模式的多个存储装置的模式的电路包括配置成保持存储器访问的命令队列，以及取消单元，被配置为取消对至少一个存储器访问的存储器访问的目标设备的省电模式 命令队列的预定阶段。

公开(公告)号：US20100287391A1

公开(公告)日：2010-11-11

申请号：US12774266

申请日：2010-05-05

申请人： Wataru Ochiai

发明人： Wataru Ochiai

IPC分类号： G06F1/32 ,  G06F12/00

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G06F13/1668 ,  Y02D10/13 ,  Y02D10/14

摘要： A circuit configured to change a mode of a plurality of memory devices having a power saving mode includes a command queue configured to hold memory access, and a cancellation unit configured to cancel the power saving mode of target devices of the memory access held up to a predetermined stage of the command queue.

摘要翻译： 配置为改变具有省电模式的多个存储装置的模式的电路包括配置成保持存储器访问的命令队列，以及取消单元，被配置为取消对至少一个存储器访问的存储器访问的目标设备的省电模式 命令队列的预定阶段。

公开(公告)号：US08516214B2

公开(公告)日：2013-08-20

申请号：US12208001

申请日：2008-09-10

申请人： Wataru Ochiai

发明人： Wataru Ochiai

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/00 ,  G06F13/4243

摘要： A memory access control device for controlling access to a plurality of memory devices with differing latency, controls, when performing a first access and then a second access, the timing of performing the second access, according to a memory device accessed in the first access and a memory device accessed in the second access.

摘要翻译： 一种存储器访问控制装置，用于根据在第一访问中访问的存储器装置来控制对具有不同等待时间的多个存储器件的访问，当执行第一访问然后第二访问时执行第二访问的定时，以及 在第二次访问中访问的存储设备。

公开(公告)号：US08467444B2

公开(公告)日：2013-06-18

申请号：US12484861

申请日：2009-06-15

申请人： Masayuki Odagawa ,  Wataru Ochiai ,  Akihiro Takamura

发明人： Masayuki Odagawa ,  Wataru Ochiai ,  Akihiro Takamura

IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/04

CPC分类号： H04N7/24 ,  H04N19/176 ,  H04N19/187 ,  H04N19/188 ,  H04N19/196 ,  H04N19/44 ,  H04N19/70

摘要： An information processing system for performing processing of dividing a moving image into tiles and packetizing and outputting information corresponding to each tile includes a process time measuring packet generation unit adapted to generate and transmit a process time measuring packet in which a packet sending time is set to measure a packet process time, a packet process time measuring unit adapted to measure, based on the packet sending time set in the process time measuring packet and the reception time of the process time measuring packet, the packet process time necessary for processing a packet, a determination unit adapted to determine, based on the packet process time, the timestamp of the moving image divided into the tiles, and a packetization unit adapted to execute processing of packetizing and outputting the timestamp and the information of the moving image divided into the tiles.

摘要翻译： 一种用于执行将运动图像划分成瓦片并分组并输出与每个瓦片相对应的信息的处理的信息处理系统，包括：处理时间测量分组生成单元，适于生成并发送分组发送时间设置为 测量分组处理时间，分组处理时间测量单元，基于在处理时间测量分组中设置的分组发送时间和处理时间测量分组的接收时间来测量处理分组所需的分组处理时间， 确定单元，适于基于分组处理时间确定划分为瓦片的运动图像的时间戳;以及分组单元，适用于执行分组和输出时间戳的处理以及划分为瓦片的运动图像的信息 。

公开(公告)号：US20120072681A1

公开(公告)日：2012-03-22

申请号：US13225294

申请日：2011-09-02

申请人： Makoto Fujiwara ,  Wataru Ochiai

发明人： Makoto Fujiwara ,  Wataru Ochiai

IPC分类号： G06F12/00

CPC分类号： G06F1/3225 ,  G06F1/3275 ,  G06F13/1626 ,  Y02D10/13 ,  Y02D10/14

摘要： Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory control apparatus, which is connected with a plurality of masters and a plurality of memories having a power saving mode, arbitrates memory accesses from the plurality of the masters, monitors whether each of the plurality of the memories is in the power saving state, and determines the priorities of the memory accesses according to the result of the detection of the power saving mode.

摘要翻译： 对处于省电模式的存储器件的存储器访问取决于其发布的顺序。 因此，有时缩短存储器处于省电模式的时间段，导致功率节省效果较差。 与多个主器件连接的存储器控​​制装置和具有省电模式的多个存储器来对来自多个主器件的存储器访问进行仲裁，监视多个存储器中的每一个是否处于省电状态， 并且根据省电模式的检测结果确定存储器访问的优先级。

公开(公告)号：US20090327623A1

公开(公告)日：2009-12-31

申请号：US12495052

申请日：2009-06-30

申请人： Wataru Ochiai

发明人： Wataru Ochiai

IPC分类号： G06F12/00

CPC分类号： G06F13/1668

摘要： A memory controller includes a plurality of bus interfaces and a memory controller core configured to control a command and data issued from the plurality of bus interfaces and to write or read the command and the data into and from the memory. The memory controller core includes a command control unit configured to receive a plurality of commands issued from the plurality of bus interfaces and to reorder and store the plurality of commands and a write data control unit configured to receive a plurality of pieces of write data issued from the plurality of bus interfaces in a sequence that the command control unit receives the write commands and to output the write data based on the reordered result of the command control unit. Accordingly, latency can be minimized between the memory controller and the memory and downsizing of a circuit of the memory controller can be achieved.

摘要翻译： 存储器控制器包括多个总线接口和存储器控制器核心，其被配置为控制从多个总线接口发出的命令和数据，并将命令和数据写入或读取到存储器中。 存储器控制器核心包括：命令控制单元，被配置为接收从多个总线接口发出的多个命令，并重新排列和存储多个命令;写入数据控制单元，被配置为接收从多个总线接口发出的多个写入数据 所述多个总线接口按照命令控制单元接收写入命令的顺序，并且基于命令控制单元的重新排序的结果来输出写入数据。 因此，可以在存储器控制器和存储器之间最小化延迟，并且可以实现存储器控制器的电路的小型化。