公开(公告)号：US20120092605A1

公开(公告)日：2012-04-19

申请号：US13025178

申请日：2011-02-11

申请人： Hsiao-Wei Cheng ,  Sung-Hui Lin ,  Ming-Yung Huang ,  Pin-Miao Liu ,  Wen-Shin Wu ,  Chun-Yao Huang ,  Wei-Sheng Yu

发明人： Hsiao-Wei Cheng ,  Sung-Hui Lin ,  Ming-Yung Huang ,  Pin-Miao Liu ,  Wen-Shin Wu ,  Chun-Yao Huang ,  Wei-Sheng Yu

IPC分类号： G02F1/1343

CPC分类号： G02F1/136213

摘要： A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

摘要翻译： 提供了包括扫描线，数据线，有源器件，像素电极，电容器电极线，半导体图案层和至少一个电介质层的像素结构。 有源器件电连接到扫描线和数据线。 像素电极电连接到有源器件。 电容器电极线位于像素电极下方。 在电容器电极线和像素电极之间形成第一存储电容器。 半导体图案层设置在电容器电极线和像素电极之间，像素电极电连接到半导体图案层。 在半导体图案层和电容器电极线之间形成第二存储电容器。 电介质层配置在电容电极线与像素电极之间，位于半导电图案层与电容电极线之间。

公开(公告)号：US07842954B2

公开(公告)日：2010-11-30

申请号：US12775493

申请日：2010-05-07

申请人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

发明人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

IPC分类号： H01L33/00

CPC分类号： H01L27/124 ,  H01L27/1248 ,  H01L27/1288

摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

摘要翻译： 设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。 图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。 图案化的半导体层设置在图案化的栅极绝缘层上。 第二图案化导电层设置在图案化的半导体层上。 图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。 透明导电层完全设置在基板上。 设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

公开(公告)号：US08804059B2

公开(公告)日：2014-08-12

申请号：US13025178

申请日：2011-02-11

申请人： Hsiao-Wei Cheng ,  Sung-Hui Lin ,  Ming-Yung Huang ,  Pin-Miao Liu ,  Wen-Shin Wu ,  Chun-Yao Huang ,  Wei-Sheng Yu

发明人： Hsiao-Wei Cheng ,  Sung-Hui Lin ,  Ming-Yung Huang ,  Pin-Miao Liu ,  Wen-Shin Wu ,  Chun-Yao Huang ,  Wei-Sheng Yu

IPC分类号： G02F1/1343 ,  H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L27/14 ,  H01L29/15 ,  H01L31/036

CPC分类号： G02F1/136213

摘要： A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

摘要翻译： 提供了包括扫描线，数据线，有源器件，像素电极，电容器电极线，半导体图案层和至少一个电介质层的像素结构。 有源器件电连接到扫描线和数据线。 像素电极电连接到有源器件。 电容器电极线位于像素电极下方。 在电容器电极线和像素电极之间形成第一存储电容器。 半导体图案层设置在电容器电极线和像素电极之间，像素电极电连接到半导体图案层。 在半导体图案层和电容器电极线之间形成第二存储电容器。 电介质层配置在电容电极线与像素电极之间，位于半导电图案层与电容电极线之间。

公开(公告)号：US20080116787A1

公开(公告)日：2008-05-22

申请号：US11684011

申请日：2007-03-09

申请人： Shien-Chi Hsu ,  Chin-Yuan Lin ,  Wei-Sheng Yu ,  Yi-Jun Lu ,  Shu-Ching Hsu

发明人： Shien-Chi Hsu ,  Chin-Yuan Lin ,  Wei-Sheng Yu ,  Yi-Jun Lu ,  Shu-Ching Hsu

IPC分类号： H01J1/62 ,  H01J9/00

CPC分类号： H01L27/3244 ,  H01L27/1255 ,  H01L27/322 ,  H01L27/3258 ,  H01L27/326 ,  H01L51/56

摘要： A pixel structure of active matrix organic light emitting display and method for fabricating the same are provided. In the method, a transparent electrode, an organic light emitting diode, and a reflective electrode are formed on a substrate. Subsequently, at least one switching thin film transistor, at least one driving thin film transistor, a scan line, a data line, and a storage capacitor are formed over the substrate.

摘要翻译： 提供有源矩阵有机发光显示器的像素结构及其制造方法。 在该方法中，在基板上形成透明电极，有机发光二极管和反射电极。 随后，在衬底上形成至少一个开关薄膜晶体管，至少一个驱动薄膜晶体管，扫描线，数据线和存储电容器。

公开(公告)号：US20070292998A1

公开(公告)日：2007-12-20

申请号：US11558451

申请日：2006-11-10

申请人： Wei-Sheng Yu ,  Chien-Hung Chen

发明人： Wei-Sheng Yu ,  Chien-Hung Chen

IPC分类号： H01L21/338

CPC分类号： H01L27/1288 ,  G02F1/13439 ,  G02F1/13458 ,  G02F1/136209 ,  G02F2001/136222 ,  H01L27/1214

摘要： A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain, thus the difficulty of the manufacturing process is effectively reduced.

摘要翻译： 提供薄膜晶体管阵列（TFT）基板及其制造方法。 该制造方法仅需要或甚至少于六个用于制造与滤色器图案集成的TFT阵列基板的掩模工艺。 因此，制造方法更简单，制造成本降低。 此外，制造方法不需要在诸如平坦化层或滤色器层的相对厚膜层中形成接触窗口，以将像素电极连接到源极/漏极，因此制造过程的难度 有效减少。

公开(公告)号：US08421079B2

公开(公告)日：2013-04-16

申请号：US13094832

申请日：2011-04-27

申请人： Chia-Ming Chang ,  Wei-Sheng Yu ,  Ming-Hao Chang

发明人： Chia-Ming Chang ,  Wei-Sheng Yu ,  Ming-Hao Chang

IPC分类号： H01L27/15

CPC分类号： G02F1/136213 ,  G02F2001/13606

摘要： A pixel structure having an SMII (semiconductor-metal-insulator-ITO) capacitor is provided. Specifically, a partial region of a transparent electrode layer corresponding to a semiconductor layer is removed, so as to eliminate parasitic capacitance between the transparent electrode layer and the semiconductor layer, prevent defects (e.g., waterfall, image sticking, etc.) from occurring on the display frame, and improve the display quality.

摘要翻译： 提供具有SMII（半导体 - 金属 - 绝缘体 - ITO）电容器的像素结构。 具体地说，去除与半导体层相对应的透明电极层的局部区域，以消除透明电极层与半导体层之间的寄生电容，防止发生缺陷（例如瀑布，图像残留等） 显示框架，提高显示质量。

公开(公告)号：US07612394B2

公开(公告)日：2009-11-03

申请号：US11558451

申请日：2006-11-10

申请人： Wei-Sheng Yu ,  Chien-Hung Chen

发明人： Wei-Sheng Yu ,  Chien-Hung Chen

IPC分类号： H01L21/28

CPC分类号： H01L27/1288 ,  G02F1/13439 ,  G02F1/13458 ,  G02F1/136209 ,  G02F2001/136222 ,  H01L27/1214

摘要： A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain, thus the difficulty of the manufacturing process is effectively reduced.

摘要翻译： 提供薄膜晶体管阵列（TFT）基板及其制造方法。 该制造方法仅需要或甚至少于六个用于制造与滤色器图案集成的TFT阵列基板的掩模工艺。 因此，制造方法更简单，制造成本降低。 此外，制造方法不需要在诸如平坦化层或滤色器层的相对厚膜层中形成接触窗口，以将像素电极连接到源极/漏极，因此制造过程的难度 有效减少。

公开(公告)号：US20090173943A1

公开(公告)日：2009-07-09

申请号：US12102027

申请日：2008-04-14

申请人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

发明人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

IPC分类号： H01L33/00

CPC分类号： H01L27/124 ,  H01L27/1248 ,  H01L27/1288

摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

摘要翻译： 设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。 图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。 图案化的半导体层设置在图案化的栅极绝缘层上。 第二图案化导电层设置在图案化的半导体层上。 图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。 透明导电层完全设置在基板上。 设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

公开(公告)号：US20100213464A1

公开(公告)日：2010-08-26

申请号：US12775493

申请日：2010-05-07

申请人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

发明人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

IPC分类号： H01L33/16

CPC分类号： H01L27/124 ,  H01L27/1248 ,  H01L27/1288

摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

摘要翻译： 设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。 图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。 图案化的半导体层设置在图案化的栅极绝缘层上。 第二图案化导电层设置在图案化的半导体层上。 图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。 透明导电层完全设置在基板上。 设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

公开(公告)号：US20090142864A1

公开(公告)日：2009-06-04

申请号：US12369742

申请日：2009-02-12

申请人： Wei-Sheng Yu ,  Chien-Hung Chen

发明人： Wei-Sheng Yu ,  Chien-Hung Chen

IPC分类号： H01L21/02

CPC分类号： H01L27/1288 ,  G02F1/13439 ,  G02F1/13458 ,  G02F1/136209 ,  G02F2001/136222 ,  H01L27/1214

摘要： A method for manufacturing a thin film transistor (TFT) array substrate needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain. Thus, the difficulty of the manufacturing process is effectively reduced.

摘要翻译： 制造薄膜晶体管（TFT）阵列基板的方法仅需要或甚至少于六个用于制造与滤色器图案集成的TFT阵列基板的掩模工艺。 因此，制造方法更简单，制造成本降低。 此外，制造方法不需要在诸如平坦化层或滤色器层的相对厚膜层中形成接触窗口，以将像素电极连接到源极/漏极。 因此，制造过程的难度有效降低。