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公开(公告)号：US08686884B2
公开(公告)日：2014-04-01
申请号：US13586176
申请日：2012-08-15
IPC分类号： H03M1/10
摘要： A system and method for testing digital to analog converters (DAC) in a serial interface having a comparator to receive an input signal and a local offset signal is disclosed. A first DAC selectably provides one of a global offset to the input signal during a normal mode of operation and a first test signal to the comparator during a test mode of operation. A second DAC selectably provides one of the local offset signals to the comparator during the normal mode of operation and a second test signal to the comparator during the test mode of operation. A test module may cause the first DAC to determine a first test signal to provide to the local offset input of the comparator and may cause the second DAC to incrementally change a test signal provided to the comparator.
摘要翻译： 公开了一种用于在具有用于接收输入信号和本地偏移信号的比较器的串行接口中测试数模转换器（DAC）的系统和方法。 在操作的正常模式期间，第一DAC可选地提供输入信号的全局偏移中的一个，以及在测试操作模式期间向比较器提供第一测试信号。 第二DAC在正常操作模式期间可选地将一个局部偏置信号提供给比较器，并且在测试操作模式期间将第二测试信号提供给比较器。 测试模块可以使得第一DAC确定第一测试信号以提供给比较器的本地偏移输入，并且可以使得第二DAC递增地改变提供给比较器的测试信号。
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公开(公告)号：US20140049415A1
公开(公告)日：2014-02-20
申请号：US13586176
申请日：2012-08-15
IPC分类号： H03M1/10
摘要： A system and method for testing digital to analog converters (DAC) in a serial interface having a comparator to receive an input signal and a local offset signal is disclosed. A first DAC selectably provides one of a global offset to the input signal during a normal mode of operation and a first test signal to the comparator during a test mode of operation. A second DAC selectably provides one of the local offset signals to the comparator during the normal mode of operation and a second test signal to the comparator during the test mode of operation. A test module may cause the first DAC to determine a first test signal to provide to the local offset input of the comparator and may cause the second DAC to incrementally change a test signal provided to the comparator.
摘要翻译： 公开了一种用于在具有用于接收输入信号和本地偏移信号的比较器的串行接口中测试数模转换器（DAC）的系统和方法。 在操作的正常模式期间，第一DAC可选地提供输入信号的全局偏移中的一个，以及在测试操作模式期间向比较器提供第一测试信号。 第二DAC在正常操作模式期间可选地将一个局部偏置信号提供给比较器，并且在测试操作模式期间将第二测试信号提供给比较器。 测试模块可以使得第一DAC确定第一测试信号以提供给比较器的本地偏移输入，并且可以使得第二DAC递增地改变提供给比较器的测试信号。
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公开(公告)号：US07191305B2
公开(公告)日：2007-03-13
申请号：US10952269
申请日：2004-09-28
申请人： William D. Corti , Joseph O. Marsh , Michael Won
发明人： William D. Corti , Joseph O. Marsh , Michael Won
IPC分类号： G06F12/00
CPC分类号： G11C8/04
摘要： A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.
摘要翻译： 公开了一种用于解码嵌入式DRAM（eDRAM）设备的存储器阵列地址的方法，该eDRAM器件被配置为与SDRAM存储器管理器一起操作。 在本发明的示例性实施例中，该方法包括在第一时间从存储器管理器接收一组行地址位。 随后，一组初始列地址位在稍后的时间从存储器管理器。 初始列地址位的集合被转换为一组转换的列地址位，并且行地址位集合和转换的列地址位的集合被同时用于访问eDRAM设备中期望的存储器位置。 eDRAM设备中期望的存储器位置具有对应于行地址位集合的值的行地址和对应于转换列地址位集合的值的列地址。
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公开(公告)号：US06834360B2
公开(公告)日：2004-12-21
申请号：US09683091
申请日：2001-11-16
申请人： William D. Corti , Robert Kenny, Jr. , Joseph O. Marsh , Steven C. Parker , Frank X. Scanzano , Michael Won
发明人： William D. Corti , Robert Kenny, Jr. , Joseph O. Marsh , Steven C. Parker , Frank X. Scanzano , Michael Won
IPC分类号： G06F1100
CPC分类号： G06F11/3648 , G06F11/3636
摘要： An on-chip logic analysis (OCLA) system captures data processed by a signal processing logic core embedded in a single-chip-device (SOC) without interrupting operations of the signal processing logic core. The OCLA system includes a data capturing unit embedded in the SOC device to monitor the operations of the signal processing unit and determines whether the operations satisfy predetermined trigger conditions. Once the trigger condition is satisfied, the data capturing unit captures internal data from/to the signal processing unit and transfers to an external host system. The host system controls the operations of the data capturing unit. The host system provides the captured data to an user interface for testing and debugging the operations of the SOC signal processing device.
摘要翻译： 片上逻辑分析（OCLA）系统捕获由嵌入在单芯片器件（SOC）中的信号处理逻辑核处理的数据，而不中断信号处理逻辑核的操作。 OCLA系统包括嵌入在SOC装置中的数据捕获单元，用于监视信号处理单元的操作，并确定操作是否满足预定的触发条件。 一旦满足触发条件，数据捕获单元从信号处理单元捕获内部数据并将其传送到外部主机系统。 主机系统控制数据采集单元的操作。 主机系统将捕获的数据提供给用户界面，用于测试和调试SOC信号处理设备的操作。
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公开(公告)号：US06834334B2
公开(公告)日：2004-12-21
申请号：US09940262
申请日：2001-08-28
申请人： William D. Corti , Joseph O. Marsh , Michael Won
发明人： William D. Corti , Joseph O. Marsh , Michael Won
IPC分类号： G06F1200
CPC分类号： G11C8/04
摘要： A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.
摘要翻译： 公开了一种用于解码嵌入式DRAM（eDRAM）设备的存储器阵列地址的方法，该eDRAM器件被配置为与SDRAM存储器管理器一起操作。 在本发明的示例性实施例中，该方法包括在第一时间从存储器管理器接收一组行地址位。 随后，一组初始列地址位在稍后的时间从存储器管理器。 初始列地址位的集合被转换为一组转换的列地址位，并且行地址位集合和转换的列地址位的集合被同时用于访问eDRAM设备中期望的存储器位置。 eDRAM设备中期望的存储器位置具有对应于行地址位集合的值的行地址和对应于转换列地址位集合的值的列地址。
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