公开(公告)号：US5978286A

公开(公告)日：1999-11-02

申请号：US259455

申请日：1999-03-01

申请人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

发明人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

IPC分类号： G11C7/06

CPC分类号： G11C7/06 ,  G11C7/065

摘要： A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers that are coupled to the same global data lines are enabled by clocks that are timed by a common clock signal. The memory has subarrays in which each subarray is divided into blocks. When a block is selected, a corresponding block select signal is generated. The sense amplifiers and the secondary amplifiers that are coupled in common with the enabled sense amplifiers in the selected block are enabled in response to this block select signal. The block select signal that enables the sense amplifiers initiates a secondary amp control signal which, after a programmed delay, enables the secondary amplifier.

摘要翻译： 存储器具有读出放大器，其将数据提供到由次级放大器接收的全局数据线上。 耦合到相同全局数据线的读出放大器和次级放大器由通过公共时钟信号定时的时钟使能。 存储器具有子阵列，其中每个子阵列被分成块。 当选择块时，生成相应的块选择信号。 与所选块中的使能读出放大器共同耦合的读出放大器和次级放大器响应于该块选择信号被使能。 启用读出放大器的块选择信号启动次级放大器控制信号，在编程的延迟之后，使能辅助放大器。

公开(公告)号：US06385101B1

公开(公告)日：2002-05-07

申请号：US09543532

申请日：2000-04-06

申请人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

发明人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

IPC分类号： G11C708

CPC分类号： G11C7/222 ,  G11C7/06 ,  G11C7/22 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  H03K5/131 ,  H03K5/133

摘要： A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

摘要翻译： 存储器具有读出放大器，其将数据提供到由次级放大器接收的全局数据线上。 读出放大器和次级放大器由可编程延迟电路定时的时钟使能。 可编程延迟由延迟选择电路编程，这些延迟选择电路为可编程延迟电路提供连续输出。 有两个延迟选择电路。 所有可编程延迟电路共享一个，这些可编程延迟电路使得读出放大器成为可能，并且一个被所有可使用次级放大器的可编程延迟电路共享。 选择这两个延迟选择电路的输出以提供对可编程延迟电路进行编程的输出，以优化存储器的访问时间的最坏情况。

公开(公告)号：US06111796A

公开(公告)日：2000-08-29

申请号：US259454

申请日：1999-03-01

申请人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

发明人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22

CPC分类号： G11C7/222 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C7/06 ,  G11C7/22 ,  H03K5/131 ,  H03K5/133

摘要： A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

公开(公告)号：US6044036A

公开(公告)日：2000-03-28

申请号：US78159

申请日：1998-05-13

申请人： Stephen T. Flannagan ,  William R. Weier

发明人： Stephen T. Flannagan ,  William R. Weier

IPC分类号： G11C7/10 ,  G11C8/06 ,  H03K17/041 ,  G11C8/00

CPC分类号： H03K17/04106 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/06

摘要： A buffer circuit (60) that includes a current source (74) having an output, the current source to provide a substantially constant current, a first differential amplifier (62), and a second differential amplifier (66). The current from current source 74 is shared by the first (62) and second (64) differential amplifiers.

摘要翻译： 一种缓冲电路（60），包括具有输出的电流源（74），用于提供基本恒定电流的电流源，第一差分放大器（62）和第二差分放大器（66）。 来自电流源74的电流由第一（62）和第二（64）差分放大器共用。

公开(公告)号：US6031775A

公开(公告)日：2000-02-29

申请号：US259453

申请日：1999-03-01

申请人： Ray Chang ,  William R. Weier

发明人： Ray Chang ,  William R. Weier

IPC分类号： G11C7/06

CPC分类号： G11C7/065

摘要： A memory has a sense amplifier that provides data onto a global data line that is received by a secondary amplifier. The sense amplifier is precharged to a high voltage and responds to data provided by a selected memory cell on a pair of bit lines. The amplifier is a dynamic amplifier that latches the data but also limits the output voltage swing provided to the secondary amplifier. By limiting the voltage swing on the high-capacitance global data lines, there is significant power savings. The voltage swing that is provided is sufficient for reliable detection by the secondary amplifier.

摘要翻译： 存储器具有读取放大器，其将数据提供到由辅助放大器接收的全局数据线上。 读出放大器被预充电到高电压并且响应由一对位线上的所选存储单元提供的数据。 该放大器是锁存数据的动态放大器，但也限制了提供给辅助放大器的输出电压摆幅。 通过限制高电容全局数据线上的电压摆幅，可节省大量功耗。 提供的电压摆幅足以用于辅助放大器的可靠检测。