公开(公告)号：US06385101B1

公开(公告)日：2002-05-07

申请号：US09543532

申请日：2000-04-06

申请人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

发明人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

IPC分类号： G11C708

CPC分类号： G11C7/222 ,  G11C7/06 ,  G11C7/22 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  H03K5/131 ,  H03K5/133

摘要： A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

摘要翻译： 存储器具有读出放大器，其将数据提供到由次级放大器接收的全局数据线上。 读出放大器和次级放大器由可编程延迟电路定时的时钟使能。 可编程延迟由延迟选择电路编程，这些延迟选择电路为可编程延迟电路提供连续输出。 有两个延迟选择电路。 所有可编程延迟电路共享一个，这些可编程延迟电路使得读出放大器成为可能，并且一个被所有可使用次级放大器的可编程延迟电路共享。 选择这两个延迟选择电路的输出以提供对可编程延迟电路进行编程的输出，以优化存储器的访问时间的最坏情况。

公开(公告)号：US06111796A

公开(公告)日：2000-08-29

申请号：US259454

申请日：1999-03-01

申请人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

发明人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22

CPC分类号： G11C7/222 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C7/06 ,  G11C7/22 ,  H03K5/131 ,  H03K5/133

摘要： A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

公开(公告)号：US5978286A

公开(公告)日：1999-11-02

申请号：US259455

申请日：1999-03-01

申请人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

发明人： Ray Chang ,  William R. Weier ,  Richard Y. Wong

IPC分类号： G11C7/06

CPC分类号： G11C7/06 ,  G11C7/065

摘要： A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers that are coupled to the same global data lines are enabled by clocks that are timed by a common clock signal. The memory has subarrays in which each subarray is divided into blocks. When a block is selected, a corresponding block select signal is generated. The sense amplifiers and the secondary amplifiers that are coupled in common with the enabled sense amplifiers in the selected block are enabled in response to this block select signal. The block select signal that enables the sense amplifiers initiates a secondary amp control signal which, after a programmed delay, enables the secondary amplifier.

摘要翻译： 存储器具有读出放大器，其将数据提供到由次级放大器接收的全局数据线上。 耦合到相同全局数据线的读出放大器和次级放大器由通过公共时钟信号定时的时钟使能。 存储器具有子阵列，其中每个子阵列被分成块。 当选择块时，生成相应的块选择信号。 与所选块中的使能读出放大器共同耦合的读出放大器和次级放大器响应于该块选择信号被使能。 启用读出放大器的块选择信号启动次级放大器控制信号，在编程的延迟之后，使能辅助放大器。

公开(公告)号：US6031775A

公开(公告)日：2000-02-29

申请号：US259453

申请日：1999-03-01

申请人： Ray Chang ,  William R. Weier

发明人： Ray Chang ,  William R. Weier

IPC分类号： G11C7/06

CPC分类号： G11C7/065

摘要： A memory has a sense amplifier that provides data onto a global data line that is received by a secondary amplifier. The sense amplifier is precharged to a high voltage and responds to data provided by a selected memory cell on a pair of bit lines. The amplifier is a dynamic amplifier that latches the data but also limits the output voltage swing provided to the secondary amplifier. By limiting the voltage swing on the high-capacitance global data lines, there is significant power savings. The voltage swing that is provided is sufficient for reliable detection by the secondary amplifier.

摘要翻译： 存储器具有读取放大器，其将数据提供到由辅助放大器接收的全局数据线上。 读出放大器被预充电到高电压并且响应由一对位线上的所选存储单元提供的数据。 该放大器是锁存数据的动态放大器，但也限制了提供给辅助放大器的输出电压摆幅。 通过限制高电容全局数据线上的电压摆幅，可节省大量功耗。 提供的电压摆幅足以用于辅助放大器的可靠检测。

公开(公告)号：US20090100275A1

公开(公告)日：2009-04-16

申请号：US11974699

申请日：2007-10-15

申请人： Ray Chang ,  David Ferguson

发明人： Ray Chang ,  David Ferguson

IPC分类号： G06F1/26

CPC分类号： H02J7/007 ,  G06F1/266 ,  H02J7/0052 ,  Y10T307/406

摘要： Methods and apparatus for dynamically adjusting the amount of power (or current) distributed to one or more connected devices via electrical interfaces. In one embodiment, the apparatus comprises a first module adapted to detect current drawn by a first set of ports, and a second module adapted to adjust the current provided to a second set of ports based on the detected current. The second module is also optionally adapted to distribute unreserved current among the devices according to an allocation protocol. In the exemplary context of a plurality of interconnected serial bus devices, the invention enables a device to draw more current than that required to be reserved for that device (such as to comply with a specification such as USB), yet without increasing the total amount of power which must be dedicated to the serial ports as a whole. Power supply efficiency may also be advantageously optimized.

摘要翻译： 用于通过电接口动态调整分配给一个或多个连接设备的功率（或电流）量的方法和装置。 在一个实施例中，该装置包括适于检测由第一组端口抽取的电流的第一模块，以及适于基于检测到的电流来调整提供给第二组端口的电流的第二模块。 第二模块还可选地适于根据分配协议在设备之间分配未保留的电流。 在多个互连的串行总线设备的示例性上下文中，本发明使得设备能够比不需要为该设备保留的电流（例如符合诸如USB的规范）绘制更多的电流，而不增加总量 必须专门用于整个串行端口的电源。 还可以有利地优化电源效率。

公开(公告)号：US07306487B1

公开(公告)日：2007-12-11

申请号：US11594243

申请日：2006-11-08

申请人： Ray Chang

发明人： Ray Chang

IPC分类号： H01R13/648

CPC分类号： H01R13/6461 ,  H01R13/6474 ,  H01R13/6593 ,  H01R24/64

摘要： A low crosstalk transmission connector includes a housing that houses a metal spring plate, a load bar, a terminal module and a locating frame, a cable organizer, which has an axle hole that receives a 8-wire cable and 8 wire grooves that separate the 8 insulated wires of the cable, and a metal shield that accommodates the cable organizer and has a bottom clamping plate and a top clamping plate respectively hooked on the bottom and top sides of the housing to ensure high steadity. The 4th and 6th metal contact terminals and the 1st, 2nd, 3rd, 5th, 7th and 8th metal contact terminals of the terminal module have the respective front contact portions curved in two reversed directions to reduce crosstalk noise, thereby improving transmission quality.

摘要翻译： 低串扰传输连接器包括容纳金属弹簧板，负载杆，端子模块和定位框架的壳体，电缆组织器，其具有容纳8线电缆的轴孔和8条线槽， 电缆的8根绝缘电线，以及容纳电缆组织器的金属屏蔽，并具有分别钩在外壳底部和顶部的底部夹紧板和顶部夹紧板，以确保高稳定性。 第4和第6和/或第4金属接触端子以及第1，第2，第3，第3 端子模块的第<！ - SIPO - >第五，第七和/或第八/第五金属接触端子具有相应的前接触部分弯曲成两个 反向方向以减少串扰噪声，从而提高传输质​​量。

公开(公告)号：USD553088S1

公开(公告)日：2007-10-16

申请号：US29232013

申请日：2005-06-15

申请人： Ray Chang

设计人： Ray Chang

公开(公告)号：US20070235166A1

公开(公告)日：2007-10-11

申请号：US11398165

申请日：2006-04-05

申请人： Ray Chang

发明人： Ray Chang

IPC分类号： F28D15/00

CPC分类号： H01L23/427 ,  F28D15/0266 ,  G06F1/203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Handle arrangements having an integrated heat pipe for use with a portable electronic device are presented including: a heat pipe, the heat pipe configured with a heat receiving portion, a heat conducting portion, and a heat dissipating portion; a handle disposed along an edge of the portable electronic device, the handle including a handle surface configured to enclose at least the heat dissipating portion, wherein the handle surface is vented to allow air flow across at least the heat dissipating portion; an attachment housing for attaching the handle with the portable electronic device, the attachment housing configured to enclose the heat conducting portion; and a processing unit having a contact surface, the contact surface in thermal communication with the heat receiving portion wherein the portable electronic device is configured to enclose the heat receiving portion.

摘要翻译： 本发明提供一种具有用于便携式电子装置的集成热管的手柄装置，包括：热管，配置有受热部的热管，导热部和散热部; 沿着便携式电子设备的边缘设置的手柄，所述手柄包括构造成至少封闭所述散热部分的手柄表面，其中所述手柄表面被排出以允许空气流过至少所述散热部分; 用于将所述手柄附接到所述便携式电子装置的附接壳体，所述附接壳体被构造成包围所述导热部分; 以及处理单元，其具有接触表面，所述接触表面与所述热接收部分热连通，其中所述便携式电子设备被配置为封闭所述受热部分。

公开(公告)号：US5477176A

公开(公告)日：1995-12-19

申请号：US253076

申请日：1994-06-02

申请人： Ray Chang ,  Lawrence F. Childs ,  Kenneth W. Jones ,  Donovan Raatz ,  Stephen Flannagan

发明人： Ray Chang ,  Lawrence F. Childs ,  Kenneth W. Jones ,  Donovan Raatz ,  Stephen Flannagan

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C8/10 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223 ,  G11C5/143 ,  G11C8/10 ,  H03K17/22 ,  H03K2017/226

摘要： A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.

摘要翻译： 用于存储器（20）的上电复位电路（30）包括DC模型电路（39），NBIAS校验电路（64）和NAND逻辑门（71）。 在存储器（20）的上电时提供逻辑低电源复位信号，以在时钟电路（29）和行和列预解码器/锁存器（24,27）中建立初始条件。 当电源电压，带隙参考电压和偏置电压都达到其预定电压时，上电复位电路（30）提供逻辑高的上电复位信号。 以这种方式，确保上电复位电路（30）提供逻辑低功率复位信号，直到达到所有适当的电压电平。 此外，上电复位电路为等效于地址缓冲电路（79）的DC电路建模，用于补偿过程和温度变化。

公开(公告)号：US5440515A

公开(公告)日：1995-08-08

申请号：US207517

申请日：1994-03-08

申请人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

发明人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

IPC分类号： G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22

摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

摘要翻译： 延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。 仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步， 。 塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。 延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。