公开(公告)号：US07425512B2

公开(公告)日：2008-09-16

申请号：US10721932

申请日：2003-11-25

申请人： Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, Jr. ,  Francis G. Celii

发明人： Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, Jr. ,  Francis G. Celii

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/31616 ,  H01L21/76895 ,  H01L28/55

摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。 氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。

公开(公告)号：US07192880B2

公开(公告)日：2007-03-20

申请号：US10952188

申请日：2004-09-28

申请人： William W. Dostalik, Jr.

发明人： William W. Dostalik, Jr.

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31144

摘要： The present invention provides a method for etching a substrate 100. The method includes conducting a first etch on an anti-reflective layer 170 and a portion of a hardmask layer 140, 150 to form an opening 162 in the substrate 100. The first etch is designed to be selective to a remaining portion of the hardmask layer 140, 150. A second etch, which is different from the first etch, is conducted on a remaining portion of the hardmask 140, 150, and it is designed to be less selective than the first etch to the remaining portion of the hardmask 140, 150. The first etch allows polymer to build up on the sidewalls of the opening 162, and the polymer substantially remains on the sidewalls during the second etch.

摘要翻译： 本发明提供一种蚀刻基板100的方法。 该方法包括在抗反射层170和硬掩模层140,150的一部分上进行第一蚀刻，以在衬底100中形成开口162。 第一蚀刻被设计为对硬掩模层140,150的剩余部分是选择性的。 不同于第一蚀刻的第二蚀刻在硬掩模140,150的剩余部分上进行，并且被设计成比对硬掩模140,150的剩余部分的第一蚀刻的选择性小。 第一蚀刻允许聚合物积聚在开口162的侧壁上，并且聚合物在第二次蚀刻期间基本上保留在侧壁上。

公开(公告)号：US20080303141A1

公开(公告)日：2008-12-11

申请号：US12137692

申请日：2008-06-12

申请人： K.R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, JR. ,  Francis G. Celii

发明人： K.R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, JR. ,  Francis G. Celii

IPC分类号： H01L23/535

CPC分类号： H01L21/31116 ,  H01L21/31616 ,  H01L21/76895 ,  H01L28/55

摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其它步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，蚀刻剂对氧化铝蚀刻停止层130是选择性的。氧化铝蚀刻停止层也可以用于 高级CMOS工艺的后端作为通孔蚀刻停止层。