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公开(公告)号：US07425512B2
公开(公告)日：2008-09-16
申请号：US10721932
申请日：2003-11-25
申请人： Kezhakkedath R. Udayakumar , Ted S. Moise , Scott R. Summerfelt , Martin G. Albrecht , William W. Dostalik, Jr. , Francis G. Celii
发明人： Kezhakkedath R. Udayakumar , Ted S. Moise , Scott R. Summerfelt , Martin G. Albrecht , William W. Dostalik, Jr. , Francis G. Celii
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31616 , H01L21/76895 , H01L28/55
摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。 氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。
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公开(公告)号：US20110062550A1
公开(公告)日：2011-03-17
申请号：US12718691
申请日：2010-03-05
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
摘要翻译： 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。
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3.发明授权Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化公开(公告)号：US07572698B2
公开(公告)日：2009-08-11
申请号：US11442810
申请日：2006-05-30
IPC分类号： H01L21/336
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译： 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。
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公开(公告)号：US20120228739A1
公开(公告)日：2012-09-13
申请号：US13480044
申请日：2012-05-24
IPC分类号： H01L29/92
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
摘要翻译： 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。
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5.发明申请Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化公开(公告)号：US20070281422A1
公开(公告)日：2007-12-06
申请号：US11442810
申请日：2006-05-30
IPC分类号： H01L21/336
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译： 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。
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公开(公告)号：US08779485B2
公开(公告)日：2014-07-15
申请号：US13480044
申请日：2012-05-24
IPC分类号： H01L21/02 , H01L23/48 , H01L21/768 , H01L49/02 , H01L27/115
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
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公开(公告)号：US08440508B2
公开(公告)日：2013-05-14
申请号：US12718691
申请日：2010-03-05
IPC分类号： H01L21/82 , H01L21/00 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
摘要翻译： 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。
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8.发明授权Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化公开(公告)号：US08053252B2
公开(公告)日：2011-11-08
申请号：US12502571
申请日：2009-07-14
IPC分类号： H01L47/00
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译： 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。
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9.发明授权Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化公开(公告)号：US07799582B2
公开(公告)日：2010-09-21
申请号：US12502523
申请日：2009-07-14
IPC分类号： H01L21/00
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译： 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。
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10.发明授权Semiconductor device having reduced single bit fails and a method of manufacture thereof 有权具有减少的单位故障的半导体器件及其制造方法公开(公告)号：US07772014B2
公开(公告)日：2010-08-10
申请号：US11845834
申请日：2007-08-28
IPC分类号： H01L29/92
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57
摘要： One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.
摘要翻译： 本发明的一个方面提供一种制造具有减少单位故障的FeRAM半导体器件的方法。 该方面包括在位于半导体衬底之上的电介质层内形成电接触，并在电介质层和电接触之上形成第一阻挡层。 第一阻挡层通过沉积多个阻挡层并在其沉积之后致密化每个阻挡层而形成。 这形成了具有相同元素组成的多个阻挡层的堆叠。 该方法还包括在第一阻挡层上形成第二阻挡层，并形成下电容器电极，在下电容器上形成铁电电介质层，以及在铁电介质层上形成上电容器电极。 本文还提供了通过该方法制造的装置。
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