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1.发明申请Ferroelectric capacitor having an oxide electrode template and a method of manufacture therefor 审中-公开具有氧化物电极模板的铁电电容器及其制造方法公开(公告)号：US20050230725A1
公开(公告)日：2005-10-20
申请号：US10828446
申请日：2004-04-20
IPC分类号： H01L21/00 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57 , H01L28/65 , H01L28/75
摘要： The present invention provides a ferroelectric capacitor, a method for manufacture therefor, and a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, may include a first electrode layer (162) located over a substrate (110), wherein the first electrode layer (162) includes iridium, and an oxide electrode template (164) located over the first electrode layer (162). The ferroelectric capacitor (100) may further include a ferroelectric dielectric layer (165) located over the oxide electrode template (164), and a second electrode layer (170) located over the ferroelectric dielectric layer (165).
摘要翻译： 本发明提供一种铁电电容器及其制造方法以及铁电随机存取存储器（FeRAM）器件。 铁电电容器（100）以及其他元件可以包括位于基板（110）上方的第一电极层（162），其中第一电极层（162）包括铱，以及氧化物电极模板（164） 第一电极层（162）。 铁电电容器（100）还可以包括位于氧化物电极模板（164）上方的铁电介质层（165）和位于铁电介质层（165）上方的第二电极层（170）。
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公开(公告)号：US20090233382A1
公开(公告)日：2009-09-17
申请号：US12472265
申请日：2009-05-26
IPC分类号： H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.
摘要翻译： 本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到铁电芯的居里温度附近的温度，并对衬底进行温度程序 ，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。 本发明的实施例包括在铁电体芯上方和下方扩展横截面的金属填充通孔，其增加了在冷却期间铁电芯上的热应力。
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3.发明申请公开(公告)号：US20080303141A1
公开(公告)日：2008-12-11
申请号：US12137692
申请日：2008-06-12
申请人： K.R. Udayakumar , Ted S. Moise , Scott R. Summerfelt , Martin G. Albrecht , William W. Dostalik, JR. , Francis G. Celii
发明人： K.R. Udayakumar , Ted S. Moise , Scott R. Summerfelt , Martin G. Albrecht , William W. Dostalik, JR. , Francis G. Celii
IPC分类号： H01L23/535
CPC分类号： H01L21/31116 , H01L21/31616 , H01L21/76895 , H01L28/55
摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其它步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，蚀刻剂对氧化铝蚀刻停止层130是选择性的。氧化铝蚀刻停止层也可以用于 高级CMOS工艺的后端作为通孔蚀刻停止层。
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公开(公告)号：US20050145908A1
公开(公告)日：2005-07-07
申请号：US10749668
申请日：2003-12-30
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L21/00 , H01L29/76
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectic cores during cooling.
摘要翻译： 本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到铁电芯的居里温度附近的温度，并对衬底进行温度程序 ，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。 本发明的实施例包括在铁电芯上方和下方的膨胀横截面的金属填充通孔，其在冷却期间增加铁电芯上的热应力。
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公开(公告)号：US20050112898A1
公开(公告)日：2005-05-26
申请号：US10721932
申请日：2003-11-25
申请人： K.R. Udayakumar , Ted Moise , Scott Summerfelt , Martin Albrecht , William Dostalik , Francis Celii
发明人： K.R. Udayakumar , Ted Moise , Scott Summerfelt , Martin Albrecht , William Dostalik , Francis Celii
IPC分类号： H01L21/02 , H01L21/311 , H01L21/316 , H01L21/768 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31616 , H01L21/76895 , H01L28/55
摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。 氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。
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