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    Method of fabricating CMOS transistor that prevents gate thinning
    1.
    发明授权
    Method of fabricating CMOS transistor that prevents gate thinning 有权
    制造防止栅极薄化的CMOS晶体管的方法

    公开(公告)号：US07268029B2

    公开(公告)日：2007-09-11

    申请号：US10994042

    申请日：2004-11-19

    Applicant: Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    Inventor： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    IPC: H01L21/8238

    CPC classification number: H01L21/823842 ,  H01L21/31111 ,  H01L21/31144

    Abstract: Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.

    Abstract translation: 提供一种制造CMOS晶体管的方法，其中在半导体衬底上形成用作栅极的多晶硅层之后，在多晶硅层上形成曝光n-MOS晶体管区的光刻胶图案。 使用光致抗蚀剂图案作为掩模，在n-MOS晶体管区域的多晶硅层中注入杂质，除去光致抗蚀剂图案。 如果n-MOS晶体管区域的多晶硅层通过注入杂质而损坏，则n-MOS晶体管区域的多晶硅层退火，并且p-MOS晶体管栅极和n-MOS晶体管栅极由 构图多晶硅层。 用氢氟酸（HF）溶液清洗半导体衬底，p-MOS晶体管栅极和n-MOS晶体管栅极，而不会降低n-MOS晶体管栅极的高度。

    Method of manufacturing a semiconductor device
    2.
    发明申请
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20050164455A1

    公开(公告)日：2005-07-28

    申请号：US10976680

    申请日：2004-10-28

    Applicant: Woo-Soon Jang ,  Joon Kim ,  Eun-Kuk Chung

    Inventor： Woo-Soon Jang ,  Joon Kim ,  Eun-Kuk Chung

    IPC: H01L21/336 ,  H01L21/8244 ,  H01L27/11

    CPC classification number: H01L27/11 ,  H01L27/1104

    Abstract: In a method of manufacturing a semiconductor device including independent gate patterns separated from each other, an active region is defined by forming a field region on a substrate. A gate oxide layer and a polysilicon layer are formed on the substrate. A preliminary gate pattern is formed by partially removing the polysilicon layer along a first direction by a first etching process. A spacer is formed along a side surface of the preliminary gate pattern. A number of separated gate patterns is formed by partially removing the preliminary gate pattern along a second direction crossing the first direction by a second etching process. The gate patterns overlap with the active regions and are separated from each other. Therefore, the overlap margin is increased, and the polysilicon layer is prevented from being over-etched when it is patterned to form the gate pattern.

    Abstract translation: 在制造包括彼此分离的独立栅极图案的半导体器件的方法中，通过在衬底上形成场区来限定有源区。 在基板上形成栅氧化层和多晶硅层。 通过第一蚀刻工艺沿着第一方向部分去除多晶硅层来形成初步栅极图案。 沿着初步栅极图案的侧表面形成间隔物。 通过第二蚀刻工艺沿着与第一方向交叉的第二方向部分地去除预选栅极图案来形成多个分离的栅极图案。 栅极图案与有源区域重叠并且彼此分离。 因此，重叠余量增加，并且当图案化以形成栅极图案时，防止多晶硅层被过度蚀刻。

    Method of manufacturing a semiconductor device
    4.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07049197B2

    公开(公告)日：2006-05-23

    申请号：US10976680

    申请日：2004-10-28

    Applicant: Woo-Soon Jang ,  Joon Kim ,  Eun-Kuk Chung

    Inventor： Woo-Soon Jang ,  Joon Kim ,  Eun-Kuk Chung

    IPC: H01L21/336

    CPC classification number: H01L27/11 ,  H01L27/1104

    Abstract: In a method of manufacturing a semiconductor device including independent gate patterns separated from each other, an active region is defined by forming a field region on a substrate. A gate oxide layer and a polysilicon layer are formed on the substrate. A preliminary gate pattern is formed by partially removing the polysilicon layer along a first direction by a first etching process. A spacer is formed along a side surface of the preliminary gate pattern. A number of separated gate patterns is formed by partially removing the preliminary gate pattern along a second direction crossing the first direction by a second etching process. The gate patterns overlap with the active regions and are separated from each other. Therefore, the overlap margin is increased, and the polysilicon layer is prevented from being over-etched when it is patterned to form the gate pattern.

    Abstract translation: 在制造包括彼此分离的独立栅极图案的半导体器件的方法中，通过在衬底上形成场区来限定有源区。 在基板上形成栅氧化层和多晶硅层。 通过第一蚀刻工艺沿着第一方向部分去除多晶硅层来形成初步栅极图案。 沿着初步栅极图案的侧表面形成间隔物。 通过第二蚀刻工艺沿着与第一方向交叉的第二方向部分地去除预选栅极图案来形成多个分离的栅极图案。 栅极图案与有源区域重叠并且彼此分离。 因此，重叠余量增加，并且当图案化以形成栅极图案时，防止多晶硅层被过度蚀刻。

    Method of fabricating CMOS transistor that prevents gate thinning
    5.
    发明申请
    Method of fabricating CMOS transistor that prevents gate thinning 有权
    制造防止栅极薄化的CMOS晶体管的方法

    公开(公告)号：US20050112814A1

    公开(公告)日：2005-05-26

    申请号：US10994042

    申请日：2004-11-19

    Applicant: Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    Inventor： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    IPC: H01L21/311 ,  H01L21/8238 ,  H01L21/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/8234 ,  H01L21/84

    CPC classification number: H01L21/823842 ,  H01L21/31111 ,  H01L21/31144

    Abstract: Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.

    Abstract translation: 提供一种制造CMOS晶体管的方法，其中在半导体衬底上形成用作栅极的多晶硅层之后，在多晶硅层上形成曝光n-MOS晶体管区的光刻胶图案。 使用光致抗蚀剂图案作为掩模，在n-MOS晶体管区域的多晶硅层中注入杂质，除去光致抗蚀剂图案。 如果n-MOS晶体管区域的多晶硅层通过注入杂质而损坏，则n-MOS晶体管区域的多晶硅层退火，并且p-MOS晶体管栅极和n-MOS晶体管栅极由 构图多晶硅层。 用氢氟酸（HF）溶液清洗半导体衬底，p-MOS晶体管栅极和n-MOS晶体管栅极，而不会降低n-MOS晶体管栅极的高度。

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