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    Interconnect model-order reduction method
    1.
    发明申请
    Interconnect model-order reduction method 失效
    互连模型阶降序法

    公开(公告)号：US20070033549A1

    公开(公告)日：2007-02-08

    申请号：US11199026

    申请日：2005-08-08

    申请人： Chia-Chi Chu ,  Herng-Jer Lee ,  Wu-Shiung Feng ,  Chao-Kai Chang

    发明人： Chia-Chi Chu ,  Herng-Jer Lee ,  Wu-Shiung Feng ,  Chao-Kai Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： An interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms disclosed. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm. Therefore, the residual error information may be taken as a reference for the order selection scheme used in Krylov subspace model-order algorithm.

    摘要翻译： 一种用于通过使用基于迭代的Arnoldi算法来将纳米级半导体互连网络还原为原始互连网络的互连模型级降低方法。 该方法基于投影方法进行，并且已经成为有效的互连建模和模拟的必要条件。 为了选择可以有效地反映原始互连网络的基本动力学的简化模型的顺序，原始互连网络的传递函数与简化的互连模型之间的残差可能被认为是确定迭代过程应该如何 结束，这里得出的残差的解析表达式。 此外，还原互连模型的近似传递函数也可以表示为原始互连模型和一些附加扰动的相加。 扰动矩阵仅与Arnoldi算法前一步的合成矢量有关。 因此，剩余误差信息可以作为Krylov子空间模型顺序算法中使用的顺序选择方案的参考。

    Multi-point model reductions of VLSI interconnects using the rational arnoldi method with adaptive orders
    2.
    发明申请
    Multi-point model reductions of VLSI interconnects using the rational arnoldi method with adaptive orders 失效
    使用具有自适应顺序的合理arnoldi方法的VLSI互连的多点模型减少

    公开(公告)号：US20060149525A1

    公开(公告)日：2006-07-06

    申请号：US11029587

    申请日：2005-01-05

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Chao-Kai Chang

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Chao-Kai Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： The work proposes a model reduction method, the rational Arnoldi method with adaptive orders (RAMAO), to be applied to high-speed VLSI interconnect models. It is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.

    摘要翻译： 该工作提出了一种模型简化方法，将适应性顺序（RAMAO）的理性Arnoldi方法应用于高速VLSI互连模型。 它是基于经典多点Pade近似的扩展，使用理性Arnoldi迭代法。 给定一组预定的扩展点，首先推导出与每个扩展点相关的原始系统的输出时刻与低阶系统的输出时刻之间的误差的精确表达式。 在所提出的RAMAO算法的每次迭代中，将选择对应于最大输出力矩误差的扩展频率。 因此，相应的降阶模型在相同阶数的所有降阶模型中产生最大的输出矩的改进。

    Block decoding method and system capable of decoding and outputting data in a rotated direction
    3.
    发明申请
    Block decoding method and system capable of decoding and outputting data in a rotated direction 审中-公开
    能够沿旋转方向解码和输出数据的块解码方法和系统

    公开(公告)号：US20050249423A1

    公开(公告)日：2005-11-10

    申请号：US11106442

    申请日：2005-04-15

    申请人： Yu-Chu Huang ,  Yi-Che Chen ,  Chao-Kai Chang

    发明人： Yu-Chu Huang ,  Yi-Che Chen ,  Chao-Kai Chang

    IPC分类号： G06K9/36 ,  H04N7/26 ,  H04N7/30

    CPC分类号： H04N19/85 ,  H04N19/127 ,  H04N19/136 ,  H04N19/17 ,  H04N19/176 ,  H04N19/44 ,  H04N19/60 ,  H04N19/91

    摘要： A block decoding method and system capable of decoding and outputting data in a rotated direction, which has a Huffman decoding device, a zigzag device, an inverse quantizer, an inverse discrete cosine device, a data buffer and a controller. In this invention, a dynamically set decoding window is introduced to perform the complete JPEG decoding on blocks in the decoding window and the Huffman decoding on blocks out of the decoding window. When decoding and outputting one or more columns of blocks in the decoding window is complete, the decoding window is dynamically adjusted to a next location for decoding and obtaining a next column of block or a next plurality of columns of blocks.

    摘要翻译： 具有霍夫曼解码装置，曲折装置，逆量化器，反相离散余弦装置，数据缓冲器和控制器的旋转方向的解码和输出数据的块解码方法和系统。 在本发明中，引入动态设定的解码窗口，对解码窗口中的块进行完整的JPEG解码，并对解码窗口之外的块进行霍夫曼解码。 当在解码窗口中解码和输出一列或多列的块完成时，将解码窗口动态地调整到下一个位置，以便解码并获得块的下一列或下一个多列的列。

    Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization
    4.
    发明授权
    Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization 失效
    设计用于时钟偏移调度和优化的VLSI同步电路的方法

    公开(公告)号：US07562324B2

    公开(公告)日：2009-07-14

    申请号：US11595151

    申请日：2006-11-09

    申请人： Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

    发明人： Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/08 ,  G06F2217/62

    摘要： A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.

    摘要翻译： 用于设计用于时钟偏移调度和优化的VLSI的同步电路的方法来优化数字同步VLSI系统的偏移，并将偏差优化的问题公式化为二次方程式编程的问题。 为了估计可靠性，使用二次方程成本函数来分析理想的偏差值和可行解之间的误差。 在运行过程中，使用几种算法来加快运算速度，降低复杂度，而ISCAS89则用作测试电路。

    Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders
    5.
    发明授权
    Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders 失效
    使用具有自适应顺序的合理Arnoldi方法，VLSI互连的多点模型减少

    公开(公告)号：US07512525B2

    公开(公告)日：2009-03-31

    申请号：US11029587

    申请日：2005-01-05

    申请人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Chao-Kai Chang

    发明人： Herng-Jer Lee ,  Chia-Chi Chu ,  Wu-Shiung Feng ,  Chao-Kai Chang

    IPC分类号： G06F17/10

    CPC分类号： G06F17/5036

    摘要： A model reduction method utilizing the rational Arnoldi method with adaptive orders (RAMAO) is applied to high-speed VLSI interconnect models. The method is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.

    摘要翻译： 利用具有自适应阶数（RAMAO）的合理Arnoldi方法的模型简化方法被应用于高速VLSI互连模型。 该方法基于经典多点Pade近似的扩展，使用理性Arnoldi迭代法。 给定一组预定的扩展点，首先推导出与每个扩展点相关的原始系统的输出时刻与低阶系统的输出时刻之间的误差的精确表达式。 在所提出的RAMAO算法的每次迭代中，将选择对应于最大输出力矩误差的扩展频率。 因此，相应的降阶模型在相同阶数的所有降阶模型中产生最大的输出矩的改进。

    Interconnect model-order reduction method
    6.
    发明授权
    Interconnect model-order reduction method 失效
    互连模型阶降序法

    公开(公告)号：US07437689B2

    公开(公告)日：2008-10-14

    申请号：US11199026

    申请日：2005-08-08

    申请人： Chia-Chi Chu ,  Herng-Jer Lee ,  Wu-Shiung Feng ,  Chao-Kai Chang

    发明人： Chia-Chi Chu ,  Herng-Jer Lee ,  Wu-Shiung Feng ,  Chao-Kai Chang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select an order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, with analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm. Therefore, the residual error information may be taken as a reference for the order selection scheme used in Krylov subspace model-order algorithm.

    摘要翻译： 互连模型级降低方法通过使用基于迭代的Arnoldi算法将纳米级半导体互连网络作为原始互连网络减少。 该方法基于投影方法进行，并且已经成为有效的互连建模和模拟的必要条件。 为了选择可以有效地反映原始互连网络的基本动力学的简化模型的顺序，原始互连网络的传递函数与简化的互连模型之间的残差可以被认为是在确定迭代过程中的参考 应该结束，这里得到的残差的解析表达式。 此外，还原互连模型的近似传递函数也可以表示为原始互连模型和一些附加扰动的相加。 扰动矩阵仅与Arnoldi算法前一步的合成矢量有关。 因此，剩余误差信息可以作为Krylov子空间模型顺序算法中使用的顺序选择方案的参考。

    Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization
    7.
    发明申请
    Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization 失效
    设计用于时钟偏移调度和优化的VLSI同步电路的方法

    公开(公告)号：US20080115098A1

    公开(公告)日：2008-05-15

    申请号：US11595151

    申请日：2006-11-09

    申请人： Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

    发明人： Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/08 ,  G06F2217/62

    摘要： A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.

    摘要翻译： 用于设计用于时钟偏移调度和优化的VLSI的同步电路的方法来优化数字同步VLSI系统的偏移，并将偏差优化的问题公式化为二次方程式编程的问题。 为了估计可靠性，使用二次方程成本函数来分析理想的偏差值和可行解之间的误差。 在运行过程中，使用几种算法来加快运算速度，降低复杂度，而ISCAS89则用作测试电路。

    Clock tree synthesis for low power consumption and low clock skew
    8.
    发明授权
    Clock tree synthesis for low power consumption and low clock skew 有权
    时钟树合成，低功耗和低时钟偏移

    公开(公告)号：US07216322B2

    公开(公告)日：2007-05-08

    申请号：US10935670

    申请日：2004-09-07

    申请人： Ming-Hong Lai ,  Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

    发明人： Ming-Hong Lai ,  Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F1/10 ,  G06F1/32 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/84

    摘要： A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

    摘要翻译： 提出了一种低速时钟树合成方法，用于高速VLSI设计的缓冲插入，去除和调整大小。 开发的工具可以嵌入到现有的时钟树合成设计流程中，以确保满足指定数据库约束和时钟偏移约束的要求。 对于给定的时钟树网络表，缓冲区的位置信息，导线参数和缓冲区的时序和功率库都包括在内。 首先计算给定时钟树网表的缓冲延迟和线延迟。 然后，如果输入网表对于给定的约束是不可行的，则解决可行的解决方案。 最后，使用提出的方法获得满足定时规范的修改后的低功率时钟树网表。

    Clock tree synthesis for low power consumption and low clock skew
    9.
    发明申请
    Clock tree synthesis for low power consumption and low clock skew 有权
    时钟树合成，低功耗和低时钟偏移

    公开(公告)号：US20060053395A1

    公开(公告)日：2006-03-09

    申请号：US10935670

    申请日：2004-09-07

    申请人： Ming-Hong Lai ,  Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

    发明人： Ming-Hong Lai ,  Chao-Kai Chang ,  Chia-Chi Chu ,  Wu-Shiung Feng

    IPC分类号： G06F17/50 ,  G06F1/04

    CPC分类号： G06F17/5045 ,  G06F1/10 ,  G06F1/32 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/84

    摘要： A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers' timing and power library are all included. The buffer delay and wire delay of the clock tree are calculated first. Then the feasible solution is solved if the input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies the timing specifications, is obtained using our proposed method.

    摘要翻译： 提出了一种低速时钟树合成方法，用于高速VLSI设计的缓冲插入，去除和调整大小。 开发的工具可以嵌入到现有的时钟树合成设计流程中，以确保满足指定数据库约束和时钟偏移约束。 对于给定的时钟树网表，缓冲区的位置信息，导线参数和缓冲区的时序和功率库都包括在内。 首先计算时钟树的缓冲延迟和线延迟。 那么如果输入网表对于给定的约束是不可行的，则解决可行解。 最后，使用我们提出的方法获得了满足时序规范的修改后的低功率时钟树网表。