公开(公告)号：US20160227235A1

公开(公告)日：2016-08-04

申请号：US14671794

申请日：2015-03-27

申请人： Yaniv Frishman ,  Etan Shirron

发明人： Yaniv Frishman ,  Etan Shirron

IPC分类号： H04N19/423 ,  H04N19/593 ,  H04N19/85 ,  H04N19/44

CPC分类号： H04N19/423 ,  H04N19/11 ,  H04N19/132 ,  H04N19/136 ,  H04N19/137 ,  H04N19/156 ,  H04N19/172 ,  H04N19/174 ,  H04N19/593

摘要： Systems, apparatus, articles, and methods are described below including operations for wireless bandwidth (BW) reduction in an encoder.

摘要翻译： 以下描述了系统，装置，物品和方法，其中包括编码器中无线带宽（BW）减少的操作。

公开(公告)号：US08856842B2

公开(公告)日：2014-10-07

申请号：US13706685

申请日：2012-12-06

申请人： Guoqing C. Li ,  Etan Shirron ,  Yaniv Frishman ,  George R. Hayek

发明人： Guoqing C. Li ,  Etan Shirron ,  Yaniv Frishman ,  George R. Hayek

IPC分类号： H04N7/18 ,  H04N21/43 ,  H04N21/4363 ,  H04N21/41

CPC分类号： H04N21/43637 ,  H04N21/4104 ,  H04N21/4305

摘要： In a wireless video system, the clock rate for wirelessly transmitting the video data from the transmitting device should be identical to the clock rate for receiving the video data at the receiving device. But the two devices have separate clocks, whose frequencies may drift apart over time, leading the video buffer to be over run or under run. Clock synchronizing messages to prevent this may be sent at short intervals when clock synchronization is first being acquired, and at larger intervals after clock synchronization has already been achieved and is merely being maintained.

摘要翻译： 在无线视频系统中，用于从发送装置无线发送视频数据的时钟速率应与用于在接收装置处接收视频数据的时钟速率相同。 但是这两个设备具有单独的时钟，其频率可能会随着时间的推移而分离，导致视频缓冲区运行或运行不足。 当首次获取时钟同步并且在已经实现时钟同步并且仅仅被维持之后的较大间隔时，可以以短时间间隔发送用于防止这种情况的时钟同步消息。

公开(公告)号：US20140149743A1

公开(公告)日：2014-05-29

申请号：US13976332

申请日：2012-03-30

申请人： Amihai Kidron ,  Yaniv Frishman

发明人： Amihai Kidron ,  Yaniv Frishman

IPC分类号： H04L29/06

CPC分类号： H04L63/0869 ,  G06F21/85

摘要： Systems and methods are directed to a memory device that includes a plurality of memory buffers and a direct memory access (DMA) descriptor structure. The DMA descriptor structure comprises a transfer command and associated data transfer information and encryption/decryption information that is configured in a two dimensional, tree-linked structure. A DMA controller that is communicatively coupled to the memory device transfers data to/from the memory buffers and encrypts/decrypts the data based on the transfer command and data transfer information and encryption/decryption information provided by the two dimensional, tree-linked DMA descriptor structure.

摘要翻译： 系统和方法涉及包括多个存储器缓冲器和直接存储器存取（DMA）描述符结构的存储器件。 DMA描述符结构包括传输命令和相关联的数据传送信息以及以二维树结构结构配置的加密/解密信息。 通信地耦合到存储器件的DMA控制器将数据传送到/从存储器缓冲器传送数据，并且基于传输命令和数据传送信息以及由二维树链接的DMA描述符提供的加密/解密信息进行加密/解密 结构体。

公开(公告)号：US20130179929A1

公开(公告)日：2013-07-11

申请号：US13706685

申请日：2012-12-06

申请人： Guoqing C. Li ,  Etan Shirron ,  Yaniv Frishman ,  George R. Hayek

发明人： Guoqing C. Li ,  Etan Shirron ,  Yaniv Frishman ,  George R. Hayek

IPC分类号： H04N21/4363

CPC分类号： H04N21/43637 ,  H04N21/4104 ,  H04N21/4305

摘要： In a wireless video system, the clock rate for wirelessly transmitting the video data from the transmitting device should be identical to the clock rate for receiving the video data at the receiving device. But the two devices have separate clocks, whose frequencies may drift apart over time, leading the video buffer to be over run or under run. Clock synchronizing messages to prevent this may be sent at short intervals when clock synchronization is first being acquired, and at larger intervals after clock synchronization has already been achieved and is merely being maintained.

摘要翻译： 在无线视频系统中，用于从发送装置无线发送视频数据的时钟速率应与用于在接收装置处接收视频数据的时钟速率相同。 但是这两个设备具有单独的时钟，其频率可能会随着时间的推移而分离，导致视频缓冲区运行或运行不足。 当首次获取时钟同步并且在已经实现时钟同步并且仅仅被维持之后的较大间隔时，可以以短时间间隔发送用于防止这种情况的时钟同步消息。

公开(公告)号：US20140282753A1

公开(公告)日：2014-09-18

申请号：US13797861

申请日：2013-03-12

申请人： GUOQING LI ,  JEFFREY R. FOERSTER ,  YANIV FRISHMAN

发明人： GUOQING LI ,  JEFFREY R. FOERSTER ,  YANIV FRISHMAN

IPC分类号： H04N21/4363 ,  H04N21/41

CPC分类号： H04N21/2404 ,  G06F3/1462 ,  G06F11/08 ,  G06F11/1004 ,  G06K9/6215 ,  G09G5/00 ,  H03M13/09 ,  H04L1/0061 ,  H04N21/23418 ,  H04N21/4122 ,  H04N21/41407 ,  H04N21/43637 ,  H04N21/44008 ,  H04W84/12

摘要： Examples are disclosed for transmitting video content. In some examples, cyclic redundancy check (CRC) values may be added to video content for video frames to be presented or displayed in a given region of a display. Results of CRC functions for consecutive video frames that use the added CRC values may be compared to determine whether the video content for the consecutive video frames is static video content. Video content for at least one of the consecutive video frames may be withheld from being transmitted if the video content for the consecutive video frames is characterized as static video content. Multiple CRC values or different CRC values may be added to further determine whether video content for the consecutive video frames or for subsequent consecutive video frames is also characterized as static video content. Other examples are described and claimed.

摘要翻译： 公开了用于发送视频内容的示例。 在一些示例中，可以将循环冗余校验（CRC）值添加到要在显示器的给定区域中呈现或显示的视频帧的视频内容。 可以比较使用添加的CRC值的连续视频帧的CRC功能的结果，以确定连续视频帧的视频内容是否是静态视频内容。 如果用于连续视频帧的视频内容被表征为静态视频内容，则可以不连续传送连续视频帧中的至少一个的视频内容。 可以添加多个CRC值或不同的CRC值，以进一步确定连续视频帧的视频内容还是后续的连续视频帧的视频内容也被表征为静态视频内容。 其他的例子被描述和要求保护。

公开(公告)号：US20180357809A1

公开(公告)日：2018-12-13

申请号：US15721024

申请日：2017-09-29

申请人： SEAN LAWLESS ,  YANIV FRISHMAN ,  PAUL DIEFENBAUGH ,  VISHAL SINHA ,  JASON TANNER

发明人： SEAN LAWLESS ,  YANIV FRISHMAN ,  PAUL DIEFENBAUGH ,  VISHAL SINHA ,  JASON TANNER

IPC分类号： G06T15/00 ,  G06T3/00 ,  G06T1/60

CPC分类号： G06T15/005 ,  G06T1/60 ,  G06T3/0093 ,  G09G2354/00 ,  G09G2360/10 ,  G09G2360/121 ,  G09G2360/18 ,  G09G2370/16

摘要： An apparatus and method for efficient rendering and transmission of video content in a virtual reality system. For example, one embodiment of an apparatus comprises: a first frame buffer to store image frames to be transmitted to a virtual reality apparatus; tile-based image rendering circuitry and/or logic to concurrently render multiple tiles of a first image frame, wherein tiles are categorized core tiles or a peripheral tiles; tile-based transmission circuitry and/or logic to transmit a first core tile rendered to the virtual reality apparatus before one or more remaining tiles have been rendered, the tile-based transmission circuitry and/or logic to continue to transmit one or more subsequently rendered core tiles following the first tile until all core tiles have been transmitted; and the tile-based transmission circuitry and/or logic to identify a subset of peripheral tiles to be transmitted based on first coordinate/offset data and to responsively transmit the subset of peripheral tiles.

公开(公告)号：US20160088300A1

公开(公告)日：2016-03-24

申请号：US14569071

申请日：2014-12-12

申请人： YANIV FRISHMAN

发明人： YANIV FRISHMAN

IPC分类号： H04N19/124 ,  H04N19/40 ,  H04N19/172 ,  H04N19/463 ,  G09G5/14 ,  H04N19/176

CPC分类号： H04N19/124 ,  G06F3/14 ,  G09G5/39 ,  G09G2340/02 ,  G09G2352/00 ,  G09G2360/08 ,  G09G2360/122 ,  G09G2370/10 ,  G09G2370/16 ,  H04N19/146 ,  H04N19/174 ,  H04N19/436

摘要： Systems, apparatus and methods are described including operations for parallel coding for wireless displays.

摘要翻译： 描述了包括用于无线显示器的并行编码的操作的系统，装置和方法。

公开(公告)号：US09419972B2

公开(公告)日：2016-08-16

申请号：US13976332

申请日：2012-03-30

申请人： Amihai Kidron ,  Yaniv Frishman

发明人： Amihai Kidron ,  Yaniv Frishman

IPC分类号： H04L29/06 ,  G06F21/85

CPC分类号： H04L63/0869 ,  G06F21/85

摘要： Systems and methods are directed to a memory device that includes a plurality of memory buffers and a direct memory access (DMA) descriptor structure. The DMA descriptor structure comprises a transfer command and associated data transfer information and encryption/decryption information that is configured in a two dimensional, tree-linked structure. A DMA controller that is communicatively coupled to the memory device transfers data to/from the memory buffers and encrypts/decrypts the data based on the transfer command and data transfer information and encryption/decryption information provided by the two dimensional, tree-linked DMA descriptor structure.

摘要翻译： 系统和方法涉及包括多个存储器缓冲器和直接存储器存取（DMA）描述符结构的存储器件。 DMA描述符结构包括传输命令和相关联的数据传送信息以及以二维树结构结构配置的加密/解密信息。 通信地耦合到存储器件的DMA控制器将数据传送到存储器缓冲器或从存储器缓冲器传送数据，并且基于由二维树链接的DMA描述符提供的传送命令和数据传送信息和加密/解密信息来对数据进行加密/解密 结构体。

公开(公告)号：US20160227257A1

公开(公告)日：2016-08-04

申请号：US14671382

申请日：2015-03-27

申请人： Yaniv Frishman ,  Moshe Naaman

发明人： Yaniv Frishman ,  Moshe Naaman

IPC分类号： H04N19/895 ,  H04N19/80 ,  H04N19/44

CPC分类号： H04N19/895 ,  H04N19/102 ,  H04N19/164 ,  H04N19/46 ,  H04N19/65 ,  H04N21/4344 ,  H04N21/4382 ,  H04N21/44209

摘要： Systems, apparatus, articles, and methods are described below including operations for replaying old packets for concealing video decoding errors as well as operations for video decoding latency adjustment based on wireless link conditions.

摘要翻译： 下面描述系统，装置，物品和方法，包括用于重放用于隐藏视频解码错误的旧分组的操作以及基于无线链路条件的用于视频解码等待时间调整的操作。

公开(公告)号：US20140003494A1

公开(公告)日：2014-01-02

申请号：US13976141

申请日：2012-06-08

申请人： Yaniv Frishman

发明人： Yaniv Frishman

IPC分类号： H04N7/26

CPC分类号： H04N19/105 ,  H04N19/134 ,  H04N19/176

摘要： Some demonstrative embodiments include devices, systems and/or methods of video encoding. For example, a device may include an encoding selector to control a block encoder to encode current video data of at least one pixel block of a current video frame, the encoding selector is to select between a first encoding mode causing the block encoder to encode the current video data into an encoded block to be provided to a decoder, and a second encoding mode allowing the block encoder to generate an indication to indicate to the decoder that the current video data is to be decoded using video data decoded from a previous video frame, wherein the encoding selector is to select between the first and second encoding modes without using previous video data of the pixel block of the previous video frame.

摘要翻译： 一些演示实施例包括视频编码的设备，系统和/或方法。 例如，设备可以包括编码选择器，用于控制块编码器以对当前视频帧的至少一个像素块的当前视频数据进行编码，编码选择器将在导致块编码器对第一编码模式进行编码的第一编码模式之间进行选择 将当前视频数据转换为要提供给解码器的编码块，以及第二编码模式，允许块编码器产生用于向解码器指示将使用从先前视频帧解码的视频数据解码当前视频数据的指示 其中编码选择器在第一和第二编码模式之间进行选择，而不使用先前视频帧的像素块的先前视频数据。