公开(公告)号：US06230280B1

公开(公告)日：2001-05-08

申请号：US09235151

申请日：1999-01-22

申请人： Yasuhiko Okasaka

发明人： Yasuhiko Okasaka

IPC分类号： G06F104

CPC分类号： G11C7/1057 ,  G11C5/145 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/108

摘要： An internal high voltage to be used in an output circuit is generated by a plurality of charge pumps according to an externally supplied clock signal, and commonly provided to output buffers of the output circuit. In a clock synchronous semiconductor device, chip occupation area as well as current dissipation can be decreased.

摘要翻译： 根据外部提供的时钟信号，由多个电荷泵产生用于输出电路的内部高电压，并且共同地提供给输出电路的输出缓冲器。 在时钟同步半导体器件中，可以减少芯片占用面积以及电流消耗。

公开(公告)号：US5867418A

公开(公告)日：1999-02-02

申请号：US957375

申请日：1997-10-24

申请人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

发明人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

IPC分类号： H01L21/8242 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  H01L27/02 ,  H01L27/108 ,  G11C7/02

CPC分类号： H01L27/0288 ,  G11C11/4074 ,  G11C11/4076 ,  G11C5/14

摘要： For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply source only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.

摘要翻译： 对于包括在DRAM中的控制时钟信号和地址信号的每个焊盘，提供n型阱区，并且每个n型阱区仅通过第一较低电源线连接到上电源。 因此，与通过第二低电源线连接n个型阱的常规装置相比，减小了从p型阱中的电阻元件流向上部电源线的电流。 因此，可以防止对电阻元件8的损坏，并且DRAM的浪涌抗扰度增加。

公开(公告)号：US4931995A

公开(公告)日：1990-06-05

申请号：US263157

申请日：1988-10-27

申请人： Yasuhiko Okasaka ,  Toshiyuki Ogawa

发明人： Yasuhiko Okasaka ,  Toshiyuki Ogawa

IPC分类号： G11C8/04 ,  G11C11/401 ,  G11C11/4096

CPC分类号： G11C11/4096

摘要： A data writing method in a DRAM comprises the steps of bringing a row address strobe input signal into an enabling state and successively changing a signal indicative of a row address while the row address strobe input signal is in the enabling state, thereby to write data successively into a plurality of memory cells designated by the row addresses.

摘要翻译： DRAM中的数据写入方法包括以下步骤：在行地址选通输入信号处于使能状态的同时，将行地址选通输入信号变为使能状态，并依次变更表示行地址的信号，依次写入数据 转换为由行地址指定的多个存储单元。

公开(公告)号：US5708610A

公开(公告)日：1998-01-13

申请号：US602643

申请日：1996-02-16

申请人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

发明人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

IPC分类号： H01L21/8242 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L27/0288 ,  G11C11/4074 ,  G11C11/4076 ,  G11C5/14

摘要： For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply means only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.

摘要翻译： 对于包括在DRAM中的控制时钟信号和地址信号的每个焊盘，提供n型阱区，并且每个n型阱区仅通过第一较低电源线连接到上电源装置。 因此，与通过第二低电源线连接n个型阱的常规装置相比，减小了从p型阱中的电阻元件流向上部电源线的电流。 因此，可以防止对电阻元件8的损坏，并且DRAM的浪涌抗扰度增加。