公开(公告)号：US5867418A

公开(公告)日：1999-02-02

申请号：US957375

申请日：1997-10-24

申请人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

发明人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

IPC分类号： H01L21/8242 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  H01L27/02 ,  H01L27/108 ,  G11C7/02

CPC分类号： H01L27/0288 ,  G11C11/4074 ,  G11C11/4076 ,  G11C5/14

摘要： For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply source only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.

摘要翻译： 对于包括在DRAM中的控制时钟信号和地址信号的每个焊盘，提供n型阱区，并且每个n型阱区仅通过第一较低电源线连接到上电源。 因此，与通过第二低电源线连接n个型阱的常规装置相比，减小了从p型阱中的电阻元件流向上部电源线的电流。 因此，可以防止对电阻元件8的损坏，并且DRAM的浪涌抗扰度增加。

公开(公告)号：US5708610A

公开(公告)日：1998-01-13

申请号：US602643

申请日：1996-02-16

申请人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

发明人： Yasuhiko Okasaka ,  Mikio Asakura ,  Hideto Hidaka ,  Masaaki Ura ,  Fukashi Morishita

IPC分类号： H01L21/8242 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L27/0288 ,  G11C11/4074 ,  G11C11/4076 ,  G11C5/14

摘要： For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply means only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.

摘要翻译： 对于包括在DRAM中的控制时钟信号和地址信号的每个焊盘，提供n型阱区，并且每个n型阱区仅通过第一较低电源线连接到上电源装置。 因此，与通过第二低电源线连接n个型阱的常规装置相比，减小了从p型阱中的电阻元件流向上部电源线的电流。 因此，可以防止对电阻元件8的损坏，并且DRAM的浪涌抗扰度增加。

公开(公告)号：US5999464A

公开(公告)日：1999-12-07

申请号：US58885

申请日：1998-04-13

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/24

CPC分类号： G11C29/24

摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

公开(公告)号：US5970507A

公开(公告)日：1999-10-19

申请号：US676963

申请日：1996-07-08

申请人： Tetsuo Kato ,  Kiyohiro Furutani ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tetsuo Kato ,  Kiyohiro Furutani ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G06F12/00

CPC分类号： G11C11/406

摘要： In a semiconductor memory device, a self refresh cycle program circuit is provided and a refresh operation is conducted in accordance with one of the refresh cycles programmed in the refresh-cycle program circuit. The refresh cycle of the self-refresh mode is selected from a plurality of refresh-cycle types. A plurality of refresh modes allows a refresh cycle to be selected from a plurality of refresh-cycle types in accordance with a selected refresh mode.

摘要翻译： 在半导体存储器件中，提供自刷新周期程序电路，并且根据在刷新周期程序电路中编程的刷新周期之一进行刷新操作。 从多个刷新周期类型中选择自刷新模式的刷新周期。 多个刷新模式允许根据所选择的刷新模式从多个刷新周期类型中选择刷新周期。

公开(公告)号：US5969984A

公开(公告)日：1999-10-19

申请号：US124508

申请日：1998-07-29

申请人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

发明人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： H01L29/40 ,  G11C5/14 ,  G11C7/10 ,  G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0944 ,  G11C13/00

CPC分类号： G11C7/1078 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147

摘要： The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

摘要翻译： 电平转换电路包括第一电流切断电路，第二电流切断电路，电平移位电路和反相器。 第一电流切割电路包括连接到具有升压电位Vpp的节点的两个PMOS晶体管。 第二电流切断电路包括连接到接地节点的两个NMOS晶体管。 电平移位电路包括两个PMOS晶体管和两个NMOS晶体管。 在直流电流在具有升压电位Vpp的节点和接地节点之间流动之前，包括在第一电流切割电路中的任何晶体管和包括在第二电流切割电路中的任何晶体管都被截止。 因此，可以防止具有升压电位Vbb的节点与接地节点之间的电流。

公开(公告)号：US5867439A

公开(公告)日：1999-02-02

申请号：US22490

申请日：1998-02-12

申请人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani ,  Kenichi Yasuda

发明人： Mikio Asakura ,  Hideto Hidaka ,  Kiyohiro Furutani ,  Kenichi Yasuda

IPC分类号： G11C8/12 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/14 ,  G11C29/28 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C29/28 ,  G11C8/12

摘要： In a semiconductor memory device selectively implementing one of a 4K refresh cycle and a 8K refresh cycle, the positions of externally applied address signal bits are switched internally by address switching circuits such that memory cells at the same positions are selected regardless of whether the 4K refresh cycle or the 8K refresh cycle is specified according to a refresh cycle mode specify signal. As a result, by testing the device in one refresh cycle mode, the device can be checked in both refresh cycle operations, reducing the test time and making the test easier.

摘要翻译： 在选择性地实现4K刷新周期和8K刷新周期之一的半导体存储器件中，外部施加的地址信号位的位置由地址切换电路在内部切换，使得在相同位置的存储单元被选择，而不管4K刷新 循环或8K刷新周期根据刷新周期模式指定信号指定。 因此，通过在一个刷新周期模式下测试器件，可以在两个刷新周期操作中检查器件，减少测试时间并使测试更容易。

公开(公告)号：US5793686A

公开(公告)日：1998-08-11

申请号：US755930

申请日：1996-11-25

申请人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

发明人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/38 ,  G11C7/00

CPC分类号： G11C29/38 ,  G11C29/34 ,  G11C7/1051 ,  G11C7/1078

摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

公开(公告)号：US06414883B2

公开(公告)日：2002-07-02

申请号：US09860795

申请日：2001-05-21

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US06301163B1

公开(公告)日：2001-10-09

申请号：US09385582

申请日：1999-08-27

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

IPC分类号： G11C2900

CPC分类号： G11C29/24

摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

摘要翻译： 一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器 正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。 控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。 所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

公开(公告)号：US06197643B1

公开(公告)日：2001-03-06

申请号：US09338574

申请日：1999-06-23

申请人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

发明人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： H01L218234

CPC分类号： G11C7/1078 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147

摘要： The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

摘要翻译： 电平转换电路包括第一电流切断电路，第二电流切断电路，电平移位电路和反相器。 第一电流切割电路包括连接到具有升压电位Vpp的节点的两个PMOS晶体管。 第二电流切断电路包括连接到接地节点的两个NMOS晶体管。 电平移位电路包括两个PMOS晶体管和两个NMOS晶体管。 在直流电流在具有升压电位Vpp的节点和接地节点之间流动之前，包括在第一电流切割电路中的任何晶体管和包括在第二电流切割电路中的任何晶体管都被截止。 因此，可以防止具有升压电位Vbb的节点与接地节点之间的电流。