摘要:
Disclosed is a receiving device which comprises first and second AD converters for inputting a received analog signal and converting the analog signal to digital signals in response to sampling clock signals of mutually different phases, first and second adaptive equalizers for respectively receiving outputs of the first and second AD converters, third and fourth adaptive equalizers for respectively receiving outputs of the second and first AD converters, a first adder for adding the outputs of the first and second adaptive converters, a second adder for adding the outputs of the third and fourth adaptive equalizers, a first decision unit for receiving the output of the first adder, deciding a received symbol for output, and outputting a decision error, a second decision unit for receiving the output of the second adder, deciding a received symbol for output, and outputting a decision error, and a multiplexing circuit for multiplexing the received symbols output from the first and second decision units, for output. The decision error from the first decision unit is supplied to the first and second adaptive equalizers, and the decision error from the second decision unit is supplied to the third and fourth adaptive equalizers.
摘要:
Disclosed is a canceller device comprising a subcanceller for compensating the sampling phase shift of a plurality of analog-to-digital convert circuits for receiving a common input analog signal, converting the analog signal into digital signals responsive to respective sampling clock signals with different phases to each other, and for outputting the digital signals, a main canceller for canceling echo/cross-talk from the signal output from analog-to-digital convert circuits whose the sampling phase shifts have been compensated, and a compensation range selection circuit for determining the range of the sampling phase shift for being compensated by the subcanceller based on the tap coefficients of the main canceller.
摘要:
Disclosed is a canceller device comprising a subcanceller for compensating the sampling phase shift of a plurality of analog-to-digital convert circuits for receiving a common input analog signal, converting the analog signal into digital signals responsive to respective sampling clock signals with different phases to each other, and for outputting the digital signals, a main canceller for canceling echo/cross-talk from the signal output from analog-to-digital convert circuits whose the sampling phase shifts have been compensated, and a compensation range selection circuit for determining the range of the sampling phase shift for being compensated by the subcanceller based on the tap coefficients of the main canceller.
摘要:
A ringing tone signal detecting circuit detects a ringing tone signal from a received signal of the echo canceler type which is supplied from a subscriber line through a hybrid circuit. The ringing tone signal detecting circuit has a sampler for sampling the received signal at a predetermined sampling frequency, a comparator for comparing an output signal from the sampler with a predetermined threshold value and producing a binary digital signal, a plurality of first through nth delay circuits for delaying the binary digital signal from the comparator for 1 through n sampling times, respectively, and a frequency detector for detecting a ringing tone signal from the binary digital signal from the comparator and output signals from the first through nth delay circuits. The circuit has particular use in detecting the ringing tone signals in the 2B1Q signaling code scheme.
摘要:
Disclosed is a receiving device which comprises first and second AD converters for inputting a received analog signal and converting the analog signal to digital signals in response to sampling clock signals of mutually different phases, first and second adaptive equalizers for respectively receiving outputs of the first and second AD converters, third and fourth adaptive equalizers for respectively receiving outputs of the second and first AD converters, a first adder for adding the outputs of the first and second adaptive converters, a second adder for adding the outputs of the third and fourth adaptive equalizers, a first decision unit for receiving the output of the first adder, deciding a received symbol for output, and outputting a decision error, a second decision unit for receiving the output of the second adder, deciding a received symbol for output, and outputting a decision error, and a multiplexing circuit for multiplexing the received symbols output from the first and second decision units, for output. The decision error from the first decision unit is supplied to the first and second adaptive equalizers, and the decision error from the second decision unit is supplied to the third and fourth adaptive equalizers.
摘要:
A signal disconnection detection circuit has a first comparing unit for producing a signal disconnection recognition signal only when a level of the first input signal is smaller than a first threshold value; a second comparing unit for producing an incomming signal only when a level of a second input signal is larger than a second threshold value; and a counter that receives the outputs of the first and second comparing unit and starts counting up when the first comparing unit produces the signal disconnection recognition signal, determining the possibility of the signal disconnection. The counter resets the counted value and stops its operation, determining that a reception signal is not disconnected, when the second comparing unit produces the reception signal. The counter produces the signal disconnection detection signal, determining that the signal is actually disconnected, when the second comparing unit produces no incomming signal before completion of the counting up.