公开(公告)号：US08385847B2

公开(公告)日：2013-02-26

申请号：US12929940

申请日：2011-02-25

申请人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

发明人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

IPC分类号： H04B1/44

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2924/0002 ,  H01L2924/00

摘要： A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.

公开(公告)号：US08159282B2

公开(公告)日：2012-04-17

申请号：US12615525

申请日：2009-11-10

申请人： Kaoru Katoh ,  Shigeki Koya ,  Shinichiro Takatani ,  Yasushi Shigeno ,  Akishige Nakajima ,  Takashi Ogawa

发明人： Kaoru Katoh ,  Shigeki Koya ,  Shinichiro Takatani ,  Yasushi Shigeno ,  Akishige Nakajima ,  Takashi Ogawa

IPC分类号： H03K17/687

CPC分类号： H03K17/693 ,  H03K17/063

摘要： The present invention is directed to reduce increase in the level of a harmonic signal of an RF (transmission) Tx output signal at the time of supplying an RF Tx signal to a bias generation circuit of an antenna switch. A semiconductor integrated circuit includes an antenna switch having a bias generation circuit, a Tx switch, and an antenna switch having a bias generation circuit, a transmitter switch, and a receiver (Rx) switch. The on/off state of a transistor of a Tx switch coupled between a Tx port and an I/O port is controlled by a Tx control bias. The on/off state of the transistors of the Rx switch coupled between the I/O port and a receiver (Rx) port is controlled by an RX control bias. A radio frequency (RF) signal input port of the bias generation circuit is coupled to the Tx port, and a negative DC output bias generated from a DC output port can be supplied to a gate control port of transistors of the Rx switch.

摘要翻译： 本发明旨在减少在将RF Tx信号提供给天线开关的偏置产生电路时的RF（发送）Tx输出信号的谐波信号的电平的增加。 半导体集成电路包括具有偏置产生电路，Tx开关和具有偏置产生电路，发射器开关和接收器（Rx））开关的天线开关的天线开关。 耦合在Tx端口和I / O端口之间的Tx开关的晶体管的导通/截止状态由Tx控制偏置来控制。 耦合在I / O端口和接收器（Rx）端口之间的Rx开关的晶体管的开/关状态由RX控制偏置来控制。 偏置产生电路的射频（RF）信号输入端口耦合到Tx端口，并且可以将从DC输出端口产生的负DC输出偏压提供给Rx开关的晶体管的栅极控制端口。

公开(公告)号：US20110034137A1

公开(公告)日：2011-02-10

申请号：US12910071

申请日：2010-10-22

申请人： Akishige NAKAJIMA ,  Yasushi SHIGENO ,  Takashi OGAWA ,  Shinnichirou TAKATANI ,  Shinya OSAKABE ,  Tomoyuki ISHIKAWA

发明人： Akishige NAKAJIMA ,  Yasushi SHIGENO ,  Takashi OGAWA ,  Shinnichirou TAKATANI ,  Shinya OSAKABE ,  Tomoyuki ISHIKAWA

IPC分类号： H01Q11/12

CPC分类号： H04B1/006 ,  H01L27/0641 ,  H03K17/005 ,  H03K17/007 ,  H03K17/063 ,  H03K17/161 ,  H03K17/302 ,  H03K17/6871 ,  H03K17/693 ,  H03K17/72 ,  H03K2017/066 ,  H03K2217/0018

摘要： The present invention provides a semiconductor integrated circuit device and a radio frequency module realizing reduction in high-order harmonic distortion or IMD. For example, a so-called antenna switch having a plurality of transistors between an antenna terminal and a plurality of signal terminals is provided with a voltage supply circuit. The voltage supply circuit is a circuit for supplying voltage from a voltage supply terminal to at least two signal terminals in the plurality of signal terminals via resistive elements. With the configuration, antenna voltage dropped due to a leakage or the like can be boosted and, for example, transistors in an off state can be set to a deep off state.

摘要翻译： 本发明提供一种半导体集成电路器件和实现高阶谐波失真或IMD降低的射频模块。 例如，在天线端子和多个信号端子之间具有多个晶体管的所谓的天线开关设置有电压供给电路。 电压供给电路是用于经由电阻元件将电压从电压端子提供给多个信号端子中的至少两个信号端子的电路。 通过该结构，可以提高由于漏电等而导致的天线电压下降，例如，可以将关断状态的晶体管设定为深断状态。

公开(公告)号：US07269392B2

公开(公告)日：2007-09-11

申请号：US10921211

申请日：2004-08-19

申请人： Akishige Nakajima ,  Takashi Ogawa ,  Hidenori Suenaga ,  Eigo Tange ,  Shinya Osakabe ,  Yasushi Shigeno

发明人： Akishige Nakajima ,  Takashi Ogawa ,  Hidenori Suenaga ,  Eigo Tange ,  Shinya Osakabe ,  Yasushi Shigeno

IPC分类号： H04B1/44

CPC分类号： H03F3/195 ,  H03F1/0277 ,  H03F1/32 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/372 ,  H03F2200/429

摘要： There are provided a transmission/reception switching circuit which is small in insertion loss and harmonic distortion and allows an increase in the output power of a power amplifier and an electronic component for communication on which the transmission/reception switching circuit is mounted. As an element composing a transmission/reception switching circuit in a wireless communication system, series-connected FETs or a multi-gate FET are used in place of a diode. Gate resistors connected between the individual gate terminals and a control terminal are designed to have resistance values which become progressively smaller from the gate to which a highest voltage is applied toward the gate to which a lowest voltage is applied.

摘要翻译： 提供了一种插入损耗和谐波失真小的发送/接收切换电路，并且允许功率放大器和安装发送/接收切换电路的通信用电子部件的输出功率的增加。 作为构成无线通信系统中的发送/接收切换电路的元件，使用串联连接的FET或多栅极FET来代替二极管。 连接在各个栅极端子和控制端子之间的栅极电阻被设计成具有从施加最低电压的栅极施加最高电压的栅极逐渐变小的电阻值。

公开(公告)号：US20070049237A1

公开(公告)日：2007-03-01

申请号：US11511300

申请日：2006-08-29

申请人： Toshihiro Miura ,  Hitoshi Akamine ,  Yasushi Shigeno ,  Akishige Nakajima ,  Masahiro Tsuchiya

发明人： Toshihiro Miura ,  Hitoshi Akamine ,  Yasushi Shigeno ,  Akishige Nakajima ,  Masahiro Tsuchiya

IPC分类号： H04B1/44 ,  H04B1/28

CPC分类号： H04B1/48

摘要： Switching characteristics in an SPDT switch are improved to reduce the rise delay in a low power slot following after a high power slot. Control terminals of an SPDT switch are respectively provided with backflow prevention circuits. The backflow prevention circuit is configured to have two transistors and a diode. In a transmission mode, for example, when a time slot where a high power passes through transistors is followed by a time slot where a low power passes through, the electric charges accumulated in the gates of the transistors are blocked. In the case where the transistors are in the OFF state, the electric charges accumulated in the gates of the transistors are immediately discharged to allow the transistors to be completely turned OFF.

摘要翻译： SPDT开关中的开关特性得到改善，可以降低高功率插槽后的低功率插槽的上升延时。 SPDT开关的控制端子分别设有防回流电路。 防回流电路被配置为具有两个晶体管和二极管。 在传输模式中，例如，当高功率通过晶体管的时隙之后是低功率通过的时隙时，积聚在晶体管的栅极中的电荷被阻断。 在晶体管处于截止状态的情况下，立即放电晶体管的栅极中累积的电荷，使晶体管完全截止。

公开(公告)号：US08824974B2

公开(公告)日：2014-09-02

申请号：US12910071

申请日：2010-10-22

申请人： Akishige Nakajima ,  Yasushi Shigeno ,  Takashi Ogawa ,  Shinnichirou Takatani ,  Shinya Osakabe ,  Tomoyuki Ishikawa

发明人： Akishige Nakajima ,  Yasushi Shigeno ,  Takashi Ogawa ,  Shinnichirou Takatani ,  Shinya Osakabe ,  Tomoyuki Ishikawa

IPC分类号： H04B1/44

CPC分类号： H04B1/006 ,  H01L27/0641 ,  H03K17/005 ,  H03K17/007 ,  H03K17/063 ,  H03K17/161 ,  H03K17/302 ,  H03K17/6871 ,  H03K17/693 ,  H03K17/72 ,  H03K2017/066 ,  H03K2217/0018

摘要： The present invention provides a semiconductor integrated circuit device and a radio frequency module realizing reduction in high-order harmonic distortion or IMD. For example, a so-called antenna switch having a plurality of transistors between an antenna terminal and a plurality of signal terminals is provided with a voltage supply circuit. The voltage supply circuit is a circuit for supplying voltage from a voltage supply terminal to at least two signal terminals in the plurality of signal terminals via resistive elements. With the configuration, antenna voltage dropped due to a leakage or the like can be boosted and, for example, transistors in an off state can be set to a deep off state.

摘要翻译： 本发明提供一种半导体集成电路器件和实现高阶谐波失真或IMD降低的射频模块。 例如，在天线端子和多个信号端子之间具有多个晶体管的所谓的天线开关设置有电压供给电路。 电压供给电路是用于经由电阻元件将电压从电压端子提供给多个信号端子中的至少两个信号端子的电路。 通过这样的结构，能够提高由漏电等引起的天线电压下降，例如可以将处于断开状态的晶体管设定为深断状态。

公开(公告)号：US20130069708A1

公开(公告)日：2013-03-21

申请号：US13677601

申请日：2012-11-15

申请人： Shigeki Koya ,  Shinichiro Takatani ,  Takashi Ogawa ,  Akishige Nakajima ,  Yasushi Shigeno

发明人： Shigeki Koya ,  Shinichiro Takatani ,  Takashi Ogawa ,  Akishige Nakajima ,  Yasushi Shigeno

IPC分类号： H03K17/687

CPC分类号： H03K17/687 ,  H04B1/006 ,  H04B1/406 ,  H04B1/525

摘要： One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg1n-Rg3n of a near-I/O FET Qn1 near to a common input/output terminal I/O connected with an antenna are set to be higher in linearity than V-I characteristics of middle-portion gate resistances Rg3n and Rg4n of middle-portion FETs Qn3 and Qn4. Thus, even in case that an uneven RF leak signal is supplied to near-I/O gate resistances Rg1n-Rg3n, and middle-portion gate resistances Rg3n and Rg4n, the distortion of current flowing through the near-I/O gate resistances Rg1n-Rg3n near to the input/output terminal I/O can be reduced.

摘要翻译： 一个高频开关Qm提供发送和接收信号到ON，另一个高频开关Qn提供另一个系统的信号为OFF。 在另一个高频开关Qn中，设定与天线连接的公共输入输出端子I / O附近的近I / O FET Qn1的近I / O栅极电阻Rg1n-Rg3n的VI特性， 与中间部分FET Qn3和Qn4的中间部分栅极电阻Rg3n和Rg4n的VI特性的线性度相比更高。 因此，即使在向近I / O栅极电阻Rg1n-Rg3n和中间部分栅极电阻Rg3n和Rg4n提供不均匀的RF泄漏信号的情况下，流过近I / O栅极电阻Rg1n的电流的失真 可以减少靠近输入/输出端子I / O的-Rg3n。

公开(公告)号：US08330524B2

公开(公告)日：2012-12-11

申请号：US13419194

申请日：2012-03-13

申请人： Kaoru Katoh ,  Shigeki Koya ,  Shinichiro Takatani ,  Yasushi Shigeno ,  Akishige Nakajima ,  Takashi Ogawa

发明人： Kaoru Katoh ,  Shigeki Koya ,  Shinichiro Takatani ,  Yasushi Shigeno ,  Akishige Nakajima ,  Takashi Ogawa

IPC分类号： H03K6/687

CPC分类号： H03K17/693 ,  H03K17/063

摘要： A semiconductor integrated circuit which reduces and increase in the level of a harmonic signal of an RF transmission output signal at the time of supplying an RF transmission signal to a bias generation circuit of an antenna switch, including an antenna switch having a bias generation circuit, a transmitter switch, and a receiver switch. The on/off state of a transistor of the transmitter switch coupled between a transmitter port and an I/O port is controlled by a transmit control bias. The on/off state of the transistors of the receiver switch coupled between the I/O port and a receiver port is controlled by a receiver control bias. An RF signal input port of the bias generation circuit is coupled to the transmit port, and a negative DC output bias generated from a DC output port is supplied to a gate control port of transistors of the receiver switch.

摘要翻译： 一种半导体集成电路，其在将RF发送信号提供给天线开关的偏置产生电路时降低并增加RF发送输出信号的谐波信号的电平，包括具有偏置产生电路的天线开关， 发射器开关和接收器开关。 耦合在发送器端口和I / O端口之间的发送器开关的晶体管的开/关状态由发送控制偏置来控制。 耦合在I / O端口和接收器端口之间的接收器开关的晶体管的开/关状态由接收器控制偏置来控制。 偏置产生电路的RF信号输入端口耦合到发送端口，并且从DC输出端口产生的负DC输出偏置被提供给接收器开关的晶体管的栅极控制端口。

公开(公告)号：US20120081262A1

公开(公告)日：2012-04-05

申请号：US13180751

申请日：2011-07-12

申请人： Satoshi TANAKA ,  Tadashi MATSUOKA ,  Masanori IIJIMA ,  Yasushi SHIGENO

发明人： Satoshi TANAKA ,  Tadashi MATSUOKA ,  Masanori IIJIMA ,  Yasushi SHIGENO

IPC分类号： H01Q3/24

CPC分类号： H03K17/693 ,  H03K17/102 ,  H03K17/6221 ,  H03K2017/066

摘要： A switch circuit with a unit capable of improving a margin voltage without using a negative bias generation circuit is provided. A switch comprising an N-type MOSFET is used for a switch passing a signal to an antenna and a switch comprising a P-type MOSFET is used for a shunt switch grounding a signal. A common control signal is input to the gate terminal of the MOSFET constituting each switch. The inverted signal of this control signal is coupled to a ground terminal of the switch, and thus the potential of the gate terminal of each MOSFET can be set to the ground voltage.

摘要翻译： 提供一种具有能够在不使用负偏压产生电路的情况下能够提高余量电压的单元的开关电路。 包括N型MOSFET的开关用于将信号传递到天线的开关，并且包括P型MOSFET的开关用于分流开关对信号进行接地。 公共控制信号被输入到构成每个开关的MOSFET的栅极端子。 该控制信号的反相信号耦合到开关的接地端子，因此每个MOSFET的栅极端子的电位可以设置为接地电压。

公开(公告)号：US07650133B2

公开(公告)日：2010-01-19

申请号：US11511300

申请日：2006-08-29

申请人： Toshihiro Miura ,  Hitoshi Akamine ,  Yasushi Shigeno ,  Akishige Nakajima ,  Masahiro Tsuchiya

发明人： Toshihiro Miura ,  Hitoshi Akamine ,  Yasushi Shigeno ,  Akishige Nakajima ,  Masahiro Tsuchiya

IPC分类号： H04B1/16

CPC分类号： H04B1/48

摘要： Switching characteristics in an SPDT switch are improved to reduce the rise delay in a low power slot following after a high power slot. Control terminals of an SPDT switch are respectively provided with backflow prevention circuits. The backflow prevention circuit is configured to have two transistors and a diode. In a transmission mode, for example, when a time slot where a high power passes through transistors is followed by a time slot where a low power passes through, the electric charges accumulated in the gates of the transistors are blocked. In the case where the transistors are in the OFF state, the electric charges accumulated in the gates of the transistors are immediately discharged to allow the transistors to be completely turned OFF.

摘要翻译： SPDT开关中的开关特性得到改善，可以降低高功率插槽后的低功率插槽的上升延时。 SPDT开关的控制端子分别设有防回流电路。 防回流电路被配置为具有两个晶体管和二极管。 在传输模式中，例如，当高功率通过晶体管的时隙之后是低功率通过的时隙时，积聚在晶体管的栅极中的电荷被阻断。 在晶体管处于截止状态的情况下，立即放电晶体管的栅极中累积的电荷，使晶体管完全截止。