公开(公告)号：US06838717B1

公开(公告)日：2005-01-04

申请号：US09653295

申请日：2000-08-31

申请人： Allen Yen ,  Frank Yauchee Hui ,  Yifeng Winston Yan

发明人： Allen Yen ,  Frank Yauchee Hui ,  Yifeng Winston Yan

IPC分类号： H01L23/52 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A monolithic integrated circuit including a capacitor structure. In one embodiment the integrated circuit includes at least first and second levels of interconnect conductor for connection to a semiconductor layer and a stack of alternating conductive and insulative layers formed in vertical alignment with respect to an underlying plane. The stack is formed between the first and second levels of conductor. Preferably the stack includes a first conductive layer, a first insulator layer formed over the first conductive layer, a second conductive layer formed over the first insulative layer, a second insulator layer formed over the second conductive layer, and a third conductive layer formed over the second insulative layer, with the first and third conductive layers commonly connected.

摘要翻译： 包括电容器结构的单片集成电路。 在一个实施例中，集成电路包括用于连接到半导体层的至少第一和第二级别的互连导体以及相对于下面的平面垂直对准地形成的交替导电层和绝缘层的叠层。 堆叠形成在第一和第二层导体之间。 优选地，堆叠包括第一导电层，形成在第一导电层上的第一绝缘体层，形成在第一绝缘层上的第二导电层，形成在第二导电层上的第二绝缘体层，以及形成在第二导电层上的第三导电层 第二绝缘层，第一和第三导电层共同连接。

公开(公告)号：US06730601B2

公开(公告)日：2004-05-04

申请号：US10080186

申请日：2002-02-21

申请人： Edward Belden Harris ,  Yifeng Winston Yan ,  Sailesh Mansinh Merchant

发明人： Edward Belden Harris ,  Yifeng Winston Yan ,  Sailesh Mansinh Merchant

IPC分类号： H01L2144

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/76807

摘要： A method of fabricating a metal-oxide-metal capacitor in a microelectronic device is provided. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is further deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor. In one embodiment, the dielectric layer may be comprised of an oxide and the barrier layers are comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. The first conductive element is preferably comprised of copper. The capacitor dielectric may be comprised of an oxide or tantalum pentoxide, while the second conductive element may be comprised of a layer of an aluminum alloy disposed between two barrier layers, each comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. Associated apparatuses are also provided.

摘要翻译： 提供了一种在微电子器件中制造金属氧化物 - 金属电容器的方法。 首先，在沉积在微电子衬底上的电介质层的表面上形成凹部。 然后在电介质层上沉积第一阻挡层，使得第一阻挡层符合凹陷。 然后将第一导电元件沉积在第一阻挡层上，以便至少填充凹部。 第二阻挡层进一步沉积在第一导电元件上，使得第一阻挡层和第二阻挡层协作以封装第一导电元件。 因此，第一导电元件包括​​电容器的第一板。 然后在第二阻挡层上沉积电容器电介质层，随后在电容器介电层上沉积第二导电元件。 因此，第二导电元件包括​​电容器的第二板。 在一个实施例中，电介质层可以由氧化物构成，并且阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。 第一导电元件优选由铜构成。 电容器电介质可以由氧化物或五氧化二钽组成，而第二导电元件可以由设置在两个阻挡层之间的铝合金层组成，每个阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。 还提供了相关装置。

公开(公告)号：US06373087B1

公开(公告)日：2002-04-16

申请号：US09652479

申请日：2000-08-31

申请人： Edward Belden Harris ,  Yifeng Winston Yan ,  Sailesh Mansinh Merchant

发明人： Edward Belden Harris ,  Yifeng Winston Yan ,  Sailesh Mansinh Merchant

IPC分类号： H01L31119

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/76807

摘要： A method of fabricating a metal-oxide-metal capacitor in a microelectronic device is provided. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is further deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor. In one embodiment, the dielectric layer may be comprised of an oxide and the barrier layers are comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. The first conductive element is preferably comprised of copper. The capacitor dielectric may be comprised of an oxide or tantalum pentoxide, while the second conductive element may be comprised of a layer of an aluminum alloy disposed between two barrier layers, each comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. Associated apparatuses are also provided.

摘要翻译： 提供了一种在微电子器件中制造金属氧化物 - 金属电容器的方法。 首先，在沉积在微电子衬底上的电介质层的表面上形成凹部。 然后在电介质层上沉积第一阻挡层，使得第一阻挡层符合凹陷。 然后将第一导电元件沉积在第一阻挡层上，以便至少填充凹部。 第二阻挡层进一步沉积在第一导电元件上，使得第一阻挡层和第二阻挡层协作以封装第一导电元件。 因此，第一导电元件包括​​电容器的第一板。 然后在第二阻挡层上沉积电容器电介质层，随后在电容器介电层上沉积第二导电元件。 因此，第二导电元件包括​​电容器的第二板。 在一个实施例中，电介质层可以由氧化物构成，并且阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。 第一导电元件优选由铜构成。 电容器电介质可以由氧化物或五氧化二钽组成，而第二导电元件可以由设置在两个阻挡层之间的铝合金层组成，每个阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。 还提供了相关装置。

公开(公告)号：US06525358B2

公开(公告)日：2003-02-25

申请号：US09951178

申请日：2001-09-13

申请人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Yifeng Winston Yan

发明人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Yifeng Winston Yan

IPC分类号： H01L2976

CPC分类号： H01L28/60 ,  H01L21/28568

摘要： An integrated circuit capacitor includes a metal plug in a dielectric layer adjacent a substrate. The metal plug has at least one topographical defect in an uppermost surface portion thereof. A lower metal electrode overlies the dielectric layer and the metal plug. The lower metal electrode includes, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer overlies the lower metal electrode, and an upper metal electrode: overlies the capacitor dielectric layer. An advantage of this structure is that the stack of metal layers of the lower metal electrode, will prevent undesired defects at the surface of the metal plug from adversely effecting device reliability or manufacturing yield.

摘要翻译： 集成电路电容器包括邻近衬底的电介质层中的金属插塞。 金属插塞在其最上表面部分具有至少一个形貌缺陷。 下部金属电极覆盖在电介质层和金属插头上。 下部金属电极以堆叠关系包括金属层，下部金属氮化物层，铝层和上部金属氮化物层。 电容器电介质层覆盖在下金属电极上，上金属电极覆盖在电容器介电层上。 这种结构的优点是，下金属电极的金属层堆叠将防止金属插塞表面的不期望的缺陷不利地影响器件的可靠性或制造成品率。

公开(公告)号：US06323044B1

公开(公告)日：2001-11-27

申请号：US09408299

申请日：1999-09-29

申请人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Yifeng Winston Yan

发明人： Edward Belden Harris ,  Sailesh Mansinh Merchant ,  Yifeng Winston Yan

IPC分类号： H01L2100

CPC分类号： H01L28/60 ,  H01L21/28568

摘要： An integrated circuit capacitor includes a metal plug in a dielectric layer adjacent a substrate. The metal plug has at least one topographical defect in an uppermost surface portion thereof. A lower metal electrode overlies the dielectric layer and the metal plug. The lower metal electrode includes, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer overlies the lower metal electrode, and an upper metal electrode overlies the capacitor dielectric layer. An advantage of this structure is that the stack of metal layers of the lower metal electrode, will prevent undesired defects at the surface of the metal plug from adversely effecting device reliability or manufacturing yield.

摘要翻译： 集成电路电容器包括邻近衬底的电介质层中的金属插塞。 金属插塞在其最上表面部分具有至少一个形貌缺陷。 下部金属电极覆盖在电介质层和金属插头上。 下部金属电极以堆叠关系包括金属层，下部金属氮化物层，铝层和上部金属氮化物层。 电容器电介质层覆盖在下金属电极上，并且上金属电极覆盖在电容器介电层上。 这种结构的优点是，下金属电极的金属层堆叠将防止在金属插塞表面的不期望的缺陷不利地影响器件的可靠性或制造成品率。