公开(公告)号：US07955985B2

公开(公告)日：2011-06-07

申请号：US12016771

申请日：2008-01-18

Applicant: Woo Yung Jung ,  Yong Chul Shin

Inventor： Woo Yung Jung ,  Yong Chul Shin

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31144 ,  H01L21/0271 ,  H01L21/32139

Abstract: A method for fabricating a semiconductor device includes forming a target etch layer over a substrate, a first auxiliary layer over the target etch layer, an isolation layer over the first auxiliary layer, and a second auxiliary layer over the isolation layer. A first exposure process is performed, where the first auxiliary layer is in focus and the second auxiliary layer is out of focus. A second exposure process is performed, where the second auxiliary layer in focus and the first auxiliary layer is out of focus. The second auxiliary layer is developed to form first mask patterns. The isolation layer and the first auxiliary layer are etched by using the first mask patterns to form second mask patterns. The second mask patterns are developed to form third mask patterns that are used to facilitate subsequent etching of the target etch layer.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成目标蚀刻层，在目标蚀刻层上形成第一辅助层，在第一辅助层上形成隔离层，以及在隔离层上方形成第二辅助层。 执行第一曝光处理，其中第一辅助层被聚焦并且第二辅助层失焦。 执行第二曝光处理，其中聚焦的第二辅助层和第一辅助层失焦。 第二辅助层被开发以形成第一掩模图案。 通过使用第一掩模图案来蚀刻隔离层和第一辅助层以形成第二掩模图案。 第二掩模图案被开发以形成用于促进目标蚀刻层的后续蚀刻的第三掩模图案。

公开(公告)号：US5524070A

公开(公告)日：1996-06-04

申请号：US290173

申请日：1994-08-15

Applicant: Yong-Chul Shin ,  Ramalingam Sridhar ,  Sargur N. Srihari ,  Victor Demjanenko

Inventor： Yong-Chul Shin ,  Ramalingam Sridhar ,  Sargur N. Srihari ,  Victor Demjanenko

IPC: G06K9/38 ,  G06T5/20 ,  G06K9/40

CPC classification number: G06T5/20 ,  G06K9/38 ,  G06K2209/01

Abstract: In a mail sorting system 10, output pixel intensities of an optical scanner 18 have their contrast locally enhanced. A contrast enhancer 24 uses statistical methods (averaging, standard deviation) coupled with empirical stretch and offset data stored in a ROM 25, to enhance pixel contrast in a pipelined processing operation.

Abstract translation: 在邮件分类系统10中，光学扫描器18的输出像素强度具有局部增强的对比度。 对比增强器24使用与存储在ROM 25中的经验拉伸和偏移数据相结合的统计方法（平均，标准偏差），以增强流水线处理操作中的像素对比度。

公开(公告)号：US20120112362A1

公开(公告)日：2012-05-10

申请号：US13290379

申请日：2011-11-07

Applicant: Yong Chul SHIN

Inventor： Yong Chul SHIN

IPC: H01L23/522 ,  H01L21/76 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in parallel between the first line pattern and the second line pattern, fourth line patterns formed in parallel between the first line pattern and the second line pattern, a first connection structure configured to couple a first of the third line patterns with a first of the fourth lines patterns, which are adjacent to the first line pattern, and a second connection structure configured to couple a second of the first lines patterns with a second of the fourth lines patterns, which are adjacent to the second line pattern.

Abstract translation: 半导体器件包括在半导体衬底上平行形成的第一线图形和第二线图案，平行形成在第一线图案和第二线图案之间的第三线图案，第一线图案和 所述第二线图案，被配置为将所述第三线图案中的第一线图案与所述第一线图案相邻的所述第四线图案中的第一线图案耦合的第一连接结构;以及第二连接结构， 具有与第二线图案相邻的第四线图案中的第二线图案的线图案。

公开(公告)号：US20090186477A1

公开(公告)日：2009-07-23

申请号：US12345612

申请日：2008-12-29

Applicant: Yong Chul SHIN ,  Tae Kyung KIM

Inventor： Yong Chul SHIN ,  Tae Kyung KIM

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76802 ,  H01L23/485 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming metal wirings of a nonvolatile memory device include forming a first insulating layer over a semiconductor substrate including a first junction area and a second junction area, forming first and second contact holes through which the first and second junction areas are respectively exposed in the first insulating layer, forming first and second contact plugs within the first and second contact holes, etching a part of the second contact plug, thus forming a recess, forming a second insulating layer to fill the recess, forming a third insulating layer over the semiconductor substrate including the first and second insulating layers, forming a first trench through which the first contact plug is exposed a second trench through which the second contact plug is exposed by etching the third insulating layer, and forming first and second metal wirings within the first and second trenches, respectively.

Abstract translation: 形成非易失性存储器件的金属配线的方法包括在包括第一接合区域和第二接合区域的半导体衬底上形成第一绝缘层，形成第一和第二接触孔，第一和第二接合区域分别通过该接触孔暴露在 第一绝缘层，在第一和第二接触孔内形成第一和第二接触塞，蚀刻第二接触塞的一部分，从而形成凹陷，形成第二绝缘层以填充凹部，在第 包括所述第一和第二绝缘层的半导体衬底，形成第一沟槽，所述第一接触插塞通过所述第一沟槽露出第二沟槽，所述第二接触插塞通过蚀刻所述第三绝缘层而暴露在所述第二沟槽中;以及在所述第一沟槽内形成第一和第二金属布线 和第二个沟槽。

公开(公告)号：US20050074892A1

公开(公告)日：2005-04-07

申请号：US10613855

申请日：2003-07-03

Applicant: Si-Hyoung Lee ,  Eun-Sun Wang ,  Eun-Jung Kim ,  John Jeon ,  Yong-Chul Shin

Inventor： Si-Hyoung Lee ,  Eun-Sun Wang ,  Eun-Jung Kim ,  John Jeon ,  Yong-Chul Shin

IPC: C12N15/10 ,  C12N15/74

CPC classification number: C12N15/102

Abstract: A method for evolving a polypeptide or a polynucleotide coding therefor, which comprises preparing a library of mutant polynucleotides through transposon-mediated random substitution, insertion or deletion of a multiple of three nucleotides on a polynucleotide coding for a target protein, expressing the mutant polynucleotides in a host cell and screening for a polypeptide having a desired property.

Abstract translation: 一种用于进化多肽或其编码多核苷酸的方法，其包括通过转座子介导的随机取代，编码靶蛋白的多核苷酸插入或缺失多个三核苷酸来编码突变体多核苷酸文库，将多核苷酸表达突变型多核苷酸 宿主细胞并筛选具有所需性质的多肽。

公开(公告)号：US06329106B1

公开(公告)日：2001-12-11

申请号：US09393868

申请日：1999-09-10

Applicant: Sang Man Bae ,  Yong Chul Shin ,  Young Mo Koo ,  Kwang Yoon Koh ,  Bong Ho Kim ,  Dong Jun Ahn

Inventor： Sang Man Bae ,  Yong Chul Shin ,  Young Mo Koo ,  Kwang Yoon Koh ,  Bong Ho Kim ,  Dong Jun Ahn

IPC: G03F900

CPC classification number: G03F1/32 ,  G03F1/74

Abstract: The present invention is directed to prevent generating repair by-products during a repair process of a phase shift mask, and defects on a quartz substrate. According to the present invention, a repair method for phase shift mask in a semiconductor device so as to remove a bridge formed between a phase shift layer on a quartz substrate, comprises the steps of: first repairing the bridge by implanting a charging ion according to a focused ion beam(“FIB”) method; and second repairing the first repaired bridge portion by emitting laser and then removing the bridge.

Abstract translation: 本发明旨在防止在相移掩模的修复过程中产生修复副产物，并且在石英衬底上产生缺陷。根据本发明，一种用于半导体器件中的相移掩模的修复方法，以便去除 形成在石英衬底上的相移层之间的桥包括以下步骤：首先通过根据聚焦离子束（“FIB”）方法注入充电离子来修复桥; 并且通过发射激光器然后去除桥接件来修复第一修复的桥接部分。

公开(公告)号：US5336937A

公开(公告)日：1994-08-09

申请号：US937804

申请日：1992-08-28

Applicant: Ramalingam Sridhar ,  Seokjin Kim ,  Yong-Chul Shin ,  Naidu C. R. Bogineni

Inventor： Ramalingam Sridhar ,  Seokjin Kim ,  Yong-Chul Shin ,  Naidu C. R. Bogineni

IPC: G06N3/063 ,  H03K19/20 ,  H03K19/0944

CPC classification number: G06N3/0635 ,  G06N3/063

Abstract: An analog synapse circuit for an artificial neural network requiring less circuitry and interconnections than prior synapses, while affording better weight programming means uses two complementary floating-gate MOSFETs with tunneling injection in an inverter configuration, with each MOSFET storing a weight value. This weight value is set by storing a charge injected by Fowler-Nordheim tunneling, or other tunneling means, into the floating-gate, which shifts the threshold voltage of the device. A programming line applies a current pulse to the MOSFET floating gate to write or erase this stored charge, thereby adjusting the weight of the MOSFET. The two MOSFETs are connected with the gate electrodes connected together and the drain electrodes connected together to provide a common gate and common drain between the two MOSFETs. An input line is connected to the common gate, and an output line is connected to the common drain. The source electrodes of each MOSFET are connected to reference voltages. The synapse circuit may be used in either a feedforword or feedback network, and may be expanded from two to four quadrant operation. The synapse provides a single output current line which represents a function of the input voltage and the stored weights. A plurality of such synapses may be configured in a network, wherein the output lines of each synapse are connected at a current summing node at the input of a neuron. An active load in the input of the neuron allows for both excitatory and inhibitory output current from the synapse circuit.

Abstract translation: 一种用于人造神经网络的模拟突触电路，其需要比先前突触更少的电路和互连，同时提供更好的权重编程装置，在逆变器配置中使用具有隧道注入的两个互补浮置栅极MOSFET，每个MOSFET存储权重值。 通过将由Fowler-Nordheim隧道或其它隧道装置注入的电荷存储到浮动栅极中来设定该重量值，该漂移栅极移动装置的阈值电压。 编程线将电流脉冲施加到MOSFET浮动栅极以写入或擦除该存储的电荷，从而调整MOSFET的重量。 两个MOSFET与连接在一起的栅电极和连接在一起的漏电极连接，以在两个MOSFET之间提供公共栅极和公共漏极。 输入线连接到公共栅极，并且输出线连接到公共漏极。 每个MOSFET的源电极连接到参考电压。 突触电路可以用于馈送语言或反馈网络，并且可以从两个扩展到四个象限操作。 突触提供单个输出电流线，其表示输入电压和存储的权重的函数。 可以在网络中配置多个这样的突触，其中每个突触的输出线在神经元的输入处的当前求和节点处连接。 神经元输入中的有效负载允许来自突触电路的兴奋性和抑制性输出电流。

公开(公告)号：US5257220A

公开(公告)日：1993-10-26

申请号：US850644

申请日：1992-03-13

Applicant: Yong-Chul Shin ,  Ramalingam Sridhar ,  Victor Demjanenko ,  Paul W. Palumbo ,  Sargur N. Srihari

Inventor： Yong-Chul Shin ,  Ramalingam Sridhar ,  Victor Demjanenko ,  Paul W. Palumbo ,  Sargur N. Srihari

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: A digital data memory unit and memory unit array, each unit of which can be searched in accordance with the contents thereof and updated, utilizes a digital storage element in the form of a register, latch, or memory cell, a comparator and control logic. Data is presented to the units in parallel on data lines and compare data is supplied in parallel to the units along other data lines. Parallel search of data in each unit, with multiple updates in units where the stored data matches the compare data, occurs rapidly and in one clock cycle (e.g., approximately 50 nanoseconds). The control logic responds to a match output from the comparator and an update enable pulse to enable a new data word on the data lines to be written into the digital storage element of the unit. The memory unit array is useful in image processing for storing pixel values and searching and updating these values in the process of image analysis to recognize certain images.

Abstract translation: 数字数据存储器单元和存储器单元阵列，其每个单元可以根据其内容进行搜索并更新，利用寄存器，锁存器或存储器单元，比较器和控制逻辑形式的数字存储元件。 数据在数据线上并行提供给单元，并且比较数据与其他数据线的单元并行提供。 在存储的数据与比较数据匹配的单位中以多个更新为单位进行并行搜索，在一个时钟周期（例如，约50纳秒）内快速发生。 控制逻辑响应来自比较器的匹配输出和更新使能脉冲，以使数据线上的新数据字能够写入该单元的数字存储元件。 存储单元阵列在用于存储像素值的图像处理中是有用的，并且在图像分析的过程中搜索和更新这些值以识别某些图像。

公开(公告)号：US20100210722A1

公开(公告)日：2010-08-19

申请号：US12682493

申请日：2008-10-07

Applicant: Yong Chul Shin ,  Myung-Sook Choi ,  Myoung-Nam Woo ,  Kyung Hwa Jung ,  Ki Seok Kim

Inventor： Yong Chul Shin ,  Myung-Sook Choi ,  Myoung-Nam Woo ,  Kyung Hwa Jung ,  Ki Seok Kim

IPC: A61K31/22 ,  C07C69/00 ,  A61P3/00

CPC classification number: A61K31/336

Abstract: The present invention relates to a composition for the prevention or treatment lipid metabolic disorders comprising fucoxanthin or marine plant extract comtaining the same as an effective indredients. Fucoxanthin or a marine plant extract comprising the same is effective in reducing weight increase and reducing triglyceride and cholesterol level in liver tissue, or plasma through inhibiting the synthesis of fatty acid and promoting the oxidation of fatty acid. Therefore, the composition comprising fucoxanthin or a marine plant extract comprising the same as an effective ingredient may be effectively used for the prevention and treatment of lipid metabolic disorders.

Abstract translation: 本发明涉及用于预防或治疗脂质代谢紊乱的组合物，其包含与有效成分相同的岩藻黄素或海洋植物提取物。 岩藻黄素或其组合物的海洋植物提取物通过抑制脂肪酸的合成和促进脂肪酸的氧化，有效降低肝组织或血浆中的甘油三酯和胆固醇水平的增加和减少。 因此，含有岩藻黄素的组合物或与有效成分相同的海洋植物提取物可以有效地用于预防和治疗脂质代谢紊乱。

公开(公告)号：US5355436A

公开(公告)日：1994-10-11

申请号：US957099

申请日：1992-10-05

Applicant: Yong-Chul Shin ,  Ramalingam Sridhar

Inventor： Yong-Chul Shin ,  Ramalingam Sridhar

IPC: G06N3/063 ,  G06F15/18

CPC classification number: G06N3/063

Abstract: A neural network provides both linearly separable and non-linearly separable logic operations, including the exclusive-or operation, on input signals in a single layer of circuits. The circuit weights the input signals with complex weights by multiplication and addition, and provides weighted signals to a neuron circuit (a neuron body or soma) which provides an output corresponding to the desired logical operation.

Abstract translation: 神经网络提供在单层电路中的输入信号上的线性可分离和非线性可分离逻辑运算，包括异或运算。 电路通过乘法和加法对具有复权重的输入信号进行加权，并向神经元电路（神经元体或神经元）提供加权信号，该神经元电路提供对应于所需逻辑运算的输出。