公开(公告)号：US08502384B2

公开(公告)日：2013-08-06

申请号：US12609925

申请日：2009-10-30

申请人： Yorio Takada ,  Kazuteru Ishizuka

发明人： Yorio Takada ,  Kazuteru Ishizuka

IPC分类号： H01L23/522

CPC分类号： H01L23/48 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.

公开(公告)号：US20120306106A1

公开(公告)日：2012-12-06

申请号：US13478211

申请日：2012-05-23

申请人： Yorio TAKADA

发明人： Yorio TAKADA

IPC分类号： H01L23/52

CPC分类号： H01L23/522 ,  H01L21/3212 ,  H01L23/34 ,  H01L27/0207 ,  H01L2023/4037 ,  H01L2023/4043 ,  H01L2023/405 ,  H01L2023/4068 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is the semiconductor substrate, wiring patterns and dummy patterns. A margin region is formed around the wiring pattern. The dummy region is further formed around the margin region. The dummy patterns are formed in the dummy region. The dummy patterns are arranged along the extending direction of the dummy region. Margin regions and dummy regions are allocated alternately with respect to the wiring pattern.

摘要翻译： 这里公开了半导体衬底，布线图案和虚拟图案。 在布线图案周围形成边缘区域。 在边缘区域周围进一步形成虚拟区域。 虚拟图案形成在虚拟区域中。 虚拟图案沿虚拟区域的延伸方向排列。 边缘区域和虚拟区域相对于布线图案交替地分配。

公开(公告)号：US20080178142A1

公开(公告)日：2008-07-24

申请号：US11907578

申请日：2007-10-15

申请人： Yorio Takada

发明人： Yorio Takada

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/78

摘要： A hotspot detection method for detecting a hotspot in a layout for a semiconductor device, includes: dividing a target analysis area into a grid based on layout data about the semiconductor device; and determining whether the grid falls into a hotspot or not, based on the results from simulation, using at least a detection criterion concerning a direction perpendicular to a direction of film thickness.

摘要翻译： 一种用于检测半导体器件的布局中的热点的热点检测方法，包括：基于关于半导体器件的布局数据，将目标分析区域划分为网格; 并且基于来自模拟的结果来确定网格是否落入热点中，至少使用关于垂直于膜厚度的方向的方向的检测标准。

公开(公告)号：US08349709B2

公开(公告)日：2013-01-08

申请号：US12782217

申请日：2010-05-18

申请人： Michio Inoue ,  Yorio Takada

发明人： Michio Inoue ,  Yorio Takada

IPC分类号： G06F17/50 ,  H01L21/46 ,  H01L21/78 ,  H01L21/31 ,  H03K19/173

CPC分类号： H01L23/5386 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/76865 ,  H01L23/528 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

摘要翻译： 图案布局方法包括以下过程。 提取半导体晶片的第一区域中的第一布线的图形数据。 第一个区域是半导体芯片形成区域。 第一区域由半导体晶片的划线区域包围。 第一个区域包括第二个区域。 第二个区域与划刻区域有界。 第二区域具有从半导体芯片形成区域和划线区域之间的边界到第一区域和第二区域之间的边界的第二距离。 布置了第一个区域中的第一个虚拟模式。 第一虚设图形具有与第一布线至少第一距离。 布置第二区域中的第二虚拟图案。 第二虚设图形具有至少距离第一布线的第一距离。 第二虚拟图形具有距离第一虚设图案至少第三距离。

公开(公告)号：US20100293515A1

公开(公告)日：2010-11-18

申请号：US12782217

申请日：2010-05-18

申请人： Michio INOUE ,  Yorio TAKADA

发明人： Michio INOUE ,  Yorio TAKADA

IPC分类号： G06F17/50

CPC分类号： H01L23/5386 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/76865 ,  H01L23/528 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

摘要翻译： 图案布局方法包括以下过程。 提取半导体晶片的第一区域中的第一布线的图形数据。 第一个区域是半导体芯片形成区域。 第一区域由半导体晶片的划线区域包围。 第一个区域包括第二个区域。 第二个区域与划刻区域有界。 第二区域具有从半导体芯片形成区域和划线区域之间的边界到第一区域和第二区域之间的边界的第二距离。 布置了第一个区域中的第一个虚拟模式。 第一虚设图形具有与第一布线至少第一距离。 布置第二区域中的第二虚拟图案。 第二虚设图形具有至少距离第一布线的第一距离。 第二虚拟图形具有距离第一虚设图案至少第三距离。

公开(公告)号：US20090144040A1

公开(公告)日：2009-06-04

申请号：US12326575

申请日：2008-12-02

申请人： Yorio TAKADA

发明人： Yorio TAKADA

IPC分类号： G06G7/48

CPC分类号： G06F17/5009

摘要： An overlap amount definition section defines an amount of overlap between divided regions when a shape prediction objective region in a polished surface formed by chemical mechanical polishing is divided into a plurality of regions. A shape prediction computation processing section divides the objective region into the plurality of regions each of which includes a region corresponding to the overlap amount defined by the overlap amount definition section, and performs computation for shape prediction on each divided region by distributed processing. A merging processing section combines the results of shape prediction on the divided regions that are calculated by the shape prediction computation processing section.

摘要翻译： 当由化学机械抛光形成的抛光表面中的形状预测目标区域被划分成多个区域时，重叠量定义部分限定分割区域之间的重叠量。 形状预测计算处理部分将目标区域划分为多个区域，每个区域包括与由重叠量定义部分定义的重叠量相对应的区域，并且通过分布式处理对每个分割区域进行形状预测的计算。 合并处理部分将通过形状预测计算处理部分计算出的分割区域的形状预测结果相结合。

公开(公告)号：US08756560B2

公开(公告)日：2014-06-17

申请号：US12213371

申请日：2008-06-18

申请人： Yorio Takada

发明人： Yorio Takada

IPC分类号： G06F17/50

CPC分类号： H01L23/49 ,  H01L21/3212 ,  H01L21/7684 ,  H01L23/522 ,  H01L24/42 ,  H01L27/0207 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A method for designing a dummy pattern that is formed in a vacant section of a chip region before a semiconductor substrate including the chip region that has a device graphics data section in which a circuit element pattern is formed and the vacant section in which the circuit element pattern is not formed is planarized by a chemical mechanical polishing process, the method includes: setting an overall dummy section on the entire chip region; setting a mesh section on the entire overall dummy section; dividing the overall dummy section by the mesh section so that a plurality of rectangular dummy patterns is formed on the entire chip region after the mesh section is set; and removing or transforming a part of the rectangular dummy patterns, thereby uniformizing a density of the dummy pattern in the chip region.

摘要翻译： 一种用于设计在包括具有其中形成电路元件图案的器件图形数据部分的芯片区域的半导体衬底之前形成在芯片区域的空白部分中的虚设图案的方法和其中电路元件 不形成图案通过化学机械抛光工艺平坦化，该方法包括：在整个芯片区域设置整个虚拟部分; 在整个虚拟部分设置网格部分; 将整个虚拟部分除以网格部分，使得在设置网格部分之后，在整个芯片区域上形成多个矩形虚拟图案; 并且去除或变换一部分矩形虚拟图案，从而使芯片区域中的虚设图形的密度均匀化。

公开(公告)号：US20140239506A1

公开(公告)日：2014-08-28

申请号：US14271781

申请日：2014-05-07

申请人： Yorio Takada ,  Kazuteru Ishizuka

发明人： Yorio Takada ,  Kazuteru Ishizuka

IPC分类号： H01L23/48

CPC分类号： H01L23/48 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.

摘要翻译： 提供一种半导体器件，包括设置在半导体衬底上的第一层，并且包括通过CMP平坦化的第一布线图案和由与第一布线图案相同的材料制成的多个第一伪图案和设置在第一布线图案上的第二层 半导体衬底，并且包括通过CMP平坦化的第二布线图案和由与第二布线图案相同的材料制成的多个第二虚设图案。 第二虚设图案中的每一个的中心轴线与垂直于半导体衬底的方向上的第一虚设图形中相应的第一虚设图案的中心轴重合。

公开(公告)号：US08073661B2

公开(公告)日：2011-12-06

申请号：US12326575

申请日：2008-12-02

申请人： Yorio Takada

发明人： Yorio Takada

IPC分类号： G06F17/10

CPC分类号： G06F17/5009

摘要： An overlap amount definition section defines an amount of overlap between divided regions when a shape prediction objective region in a polished surface formed by chemical mechanical polishing is divided into a plurality of regions. A shape prediction computation processing section divides the objective region into the plurality of regions each of which includes a region corresponding to the overlap amount defined by the overlap amount definition section, and performs computation for shape prediction on each divided region by distributed processing. A merging processing section combines the results of shape prediction on the divided regions that are calculated by the shape prediction computation processing section.

摘要翻译： 当由化学机械抛光形成的抛光表面中的形状预测目标区域被划分为多个区域时，重叠量定义部分限定分割区域之间的重叠量。 形状预测计算处理部分将目标区域划分为多个区域，每个区域包括与由重叠量定义部分定义的重叠量相对应的区域，并且通过分布式处理对每个分割区域进行形状预测的计算。 合并处理部分将通过形状预测计算处理部分计算出的分割区域的形状预测结果相结合。

公开(公告)号：US20100109163A1

公开(公告)日：2010-05-06

申请号：US12609925

申请日：2009-10-30

申请人： Yorio Takada ,  Kazuteru Ishizuka

发明人： Yorio Takada ,  Kazuteru Ishizuka

IPC分类号： H01L23/522 ,  H01L21/306

CPC分类号： H01L23/48 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate.

摘要翻译： 提供一种半导体器件，包括设置在半导体衬底上的第一层，并且包括通过CMP平坦化的第一布线图案和由与第一布线图案相同的材料制成的多个第一伪图案和设置在第一布线图案上的第二层 半导体衬底，并且包括通过CMP平坦化的第二布线图案和由与第二布线图案相同的材料制成的多个第二虚设图案。 第二虚设图案中的每一个的中心轴线与垂直于半导体衬底的方向上的第一虚设图形中相应的第一虚设图案的中心轴重合。