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1.发明申请METHOD FOR LOGIC CHECKING TO CHECK OPERATION OF CIRCUIT TO BE CONNECTED TO BUS 有权用于检查电路连接到总线的逻辑检查方法公开(公告)号：US20090210597A1
公开(公告)日：2009-08-20
申请号：US12432394
申请日：2009-04-29
IPC分类号： G06F13/00
CPC分类号： G01R31/318357 , G01R31/318314 , G06F17/5022
摘要： To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
摘要翻译： 为了检查要连接到至少一个主电路和至少一个从电路的总线的检查电路的操作，将模型连接到总线来代替主电路或从电路，并且产生给定信号 在给定的定时输出以检查要检查的电路的操作。 特别是通过多个模型的随机定时进行各种数据传送，容易使实际情况变得更加严重，能够提高检查效率。 例如，当检查总线仲裁器的操作时，代替多个主电路连接多个主机模型，以便在随机定时从每个主模型输出总线可访问性的请求，以检查总线的仲裁操作 仲裁者。
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2.发明申请ENCODING APPARATUS, ENCODING METHOD, AND COMPUTER READABLE STORAGE MEDIUM STORING PROGRAM THEREOF 审中-公开编码设备，编码方法和计算机可读存储介质存储程序公开(公告)号：US20080232456A1
公开(公告)日：2008-09-25
申请号：US12040200
申请日：2008-02-29
IPC分类号： H04B1/66
CPC分类号： G10L19/24
摘要： An encoding apparatus holds predetermined encoding conditions (sets of a sampling frequency and a bit rate) associated with predetermined ranges having consecutive possible amounts of free space in the storage 20. A set of a sampling frequency and a bit rate associated with a range corresponding to a current free capacity is selected, and sound data included in a music file generated from an original digital signal data is encoded under the encoding condition by using a predetermined encoding software. By comparing sound data restored from the encoded data and sound data included in a music file, evaluation value is calculated with an evaluation method such as PEAQ, and it is determined whether the evaluation value exceeds a threshold value. The encoded data is stored in the storage when the evaluation value exceeds the threshold value.
摘要翻译： 编码装置保持与存储器20中具有连续可能的可用空间量的预定范围相关联的预定编码条件（采样频率和比特率的集合）。 选择与对应于当前可用容量的范围相关联的采样频率和比特率的集合，并且包括在从原始数字信号数据生成的音乐文件中的声音数据在编码条件下通过使用预定的编码软件 。 通过比较从编码数据中恢复的声音数据和包含在音乐文件中的声音数据，通过诸如PEAQ的评估方法来计算评估值，并且确定评估值是否超过阈值。 当评估值超过阈值时，编码数据被存储在存储器中。
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公开(公告)号：US06636639B1
公开(公告)日：2003-10-21
申请号：US09534094
申请日：2000-03-23
申请人： Yoshihiro Terashima
发明人： Yoshihiro Terashima
IPC分类号： G06K936
CPC分类号： H04N1/2137 , H04N1/2104 , H04N1/2141 , H04N2101/00
摘要： An image recording apparatus which realizes, at low cost, both an increased number of serially sensed frames and increased speed of serial image sensing. The image recording apparatus comprises: a photoelectric converter for converting light from an object to an electric signal; a first temporary storage for temporarily storing data outputted by the photoelectric converter; an image processor for performing image processing, including compression processing, on the data read out of the first temporary storage; a second temporary storage for temporarily storing the data, on which image processing has been performed by the image processor; and a recording device for recording the data, read out of the second temporary storage, in a recording medium.
摘要翻译： 一种图像记录装置，其以低成本实现了增加的串行感测帧数量和增加的串行图像感测速度。 图像记录装置包括：光电转换器，用于将来自物体的光转换成电信号; 用于临时存储由光电转换器输出的数据的第一临时存储器; 用于对从第一临时存储器读出的数据执行包括压缩处理的图像处理的图像处理器; 用于临时存储由图像处理器执行了图像处理的数据的第二临时存储器; 以及用于将从第二临时存储器读出的数据记录在记录介质中的记录装置。
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4.发明授权公开(公告)号：US06320575B1
公开(公告)日：2001-11-20
申请号：US09184642
申请日：1998-11-03
IPC分类号： G09G500
CPC分类号： G09G3/20 , G09G3/2092 , G09G3/3611 , G09G5/006 , G09G2360/18
摘要： A memory controller comprises a first counter and a second counter, each having reset and enable functions, a vertical synch signal detector and a horizontal synch signal detector. A reset signal for the first counter is controlled by a signal detected by the vertical synch signal detector. An enable signal for the first counter and a reset signal for the second counter are controlled by a signal detected by the horizontal synch signal detector. An enable signal for the second counter is controlled in accordance with a signal indicating an image effective period. A memory address is controlled by the first and second counters.
摘要翻译： 存储器控制器包括具有复位和使能功能的第一计数器和第二计数器，垂直同步信号检测器和水平同步信号检测器。 用于第一计数器的复位信号由垂直同步信号检测器检测的信号控制。 用于第一计数器的使能信号和第二计数器的复位信号由水平同步信号检测器检测的信号控制。 根据指示图像有效期的信号来控制第二计数器的使能信号。 存储器地址由第一和第二计数器控制。
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公开(公告)号：US07738902B2
公开(公告)日：2010-06-15
申请号：US10862611
申请日：2004-06-07
IPC分类号： H04B7/00
CPC分类号： H04W52/248 , H04W52/12 , H04W52/241 , H04W52/32
摘要： Disclosed is a transmission power control method in a wireless communication system in which power allocated to a pilot signal can be varied to at least a first power and a second power. The method includes the steps of measuring reception quality using power of a receive pilot signal and power of an interference signal thereof when reception quality is measured with regard to whichever of the larger of the first power and second power is allocated; measuring reception quality using the power of the receive pilot signal and overall reception power when reception quality is measured with regard to whichever of the smaller of the first power and second power is allocated; and sending a transmission power control signal to a transmitting side in such a manner that the measured reception quality will agree with a target reception quality.
摘要翻译： 公开了一种在无线通信系统中的发送功率控制方法，其中分配给导频信号的功率可以变化至少第一功率和第二功率。 该方法包括以下步骤：当接收质量相对于分配的第一功率和第二功率中的较大者中的哪一个测量时，使用接收导频信号的功率和其干扰信号的功率来测量接收质量; 使用所述接收导频信号的功率来测量接收质量，以及当分配所述第一功率和第二功率中的较小者中的哪一个测量接收质量时的总接收功率; 以发送侧的方式发送发送功率控制信号，使得所测量的接收质量与目标接收质量一致。
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公开(公告)号：US07023413B1
公开(公告)日：2006-04-04
申请号：US09177572
申请日：1998-10-23
IPC分类号： G09G3/36
CPC分类号： G09G5/39 , G09G3/3611 , G09G2360/12 , G09G2360/128 , G09G2360/18
摘要： A system can be realized by using a single frame memory, that is costly, to allow data write and data read operations continuously without suspending the video signal input. Such a memory controller comprises a serial/parallel converter section for converting serial input data into parallel data, an FIFO memory section for temporarily storing converted data, a memory section connected to the FIFO memory section to store data for a frame and a second FIFO memory section for temporarily storing the data read out from the frame memory section. The data bit width of said memory section is made equal to n times of the bit width of said input data so that data for a number of frames up to as many as (n-2) times of the number of input pixels can be read out of said memory section for said input data while the frequency of accessing said memory section can be reduced to a half or less than a half of the video signal input frequency.
摘要翻译： 可以通过使用单个帧存储器来实现系统，这是昂贵的，以允许数据写入和数据读取操作连续而不中断视频信号输入。 这种存储器控制器包括用于将串行输入数据转换为并行数据的串行/并行转换器部分，用于临时存储转换数据的FIFO存储器部分，连接到FIFO存储器部分以存储用于帧的数据的存储器部分和第二FIFO存储器 部分，用于临时存储从帧存储器部分读出的数据。 使所述存储器部分的数据位宽度等于所述输入数据的位宽度的n倍，使得可以读取多达（n-2）倍数的输入像素数量的数据 在所述存储器部分中用于所述输入数据，而访问所述存储器部分的频率可以减少到视频信号输入频率的一半或少于一半。
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7.发明授权Method for logic checking to check operation of circuit to be connected to bus 有权用于检查要连接到总线的电路运行的逻辑检查方法公开(公告)号：US08112263B2
公开(公告)日：2012-02-07
申请号：US12432394
申请日：2009-04-29
CPC分类号： G01R31/318357 , G01R31/318314 , G06F17/5022
摘要： To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
摘要翻译： 为了检查要连接到至少一个主电路和至少一个从电路的总线的检查电路的操作，将模型连接到总线来代替主电路或从电路，并且产生给定信号 在给定的定时输出以检查要检查的电路的操作。 特别是通过多个模型的随机定时进行各种数据传送，容易使实际情况变得更加严重，能够提高检查效率。 例如，当检查总线仲裁器的操作时，代替多个主电路连接多个主机模型，以便在随机定时从每个主模型输出总线可访问性的请求，以检查总线的仲裁操作 仲裁者。
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公开(公告)号：US20100098170A1
公开(公告)日：2010-04-22
申请号：US12588409
申请日：2009-10-14
IPC分类号： H04N7/26
CPC分类号： H04N19/40 , H04N19/139 , H04N19/176 , H04N19/433 , H04N19/56 , H04N19/61
摘要： A transcoding device includes a decoding unit that decodes both motion vectors of macroblocks and images from encoded images in a first encoding format; a first decoded image storing unit that stores therein the decoded motion vectors of macroblocks and the decoded images; a vector searching unit that searches for motion vectors of macroblocks in a second encoding format by using the decoded images stored in the first decoded image storing unit as reference images and by using the decoded motion vectors stored in the first decoded image storing unit; and a motion compensating unit that reads, from the first decoded image storing unit, areas in the decoded images, which are indicated by the motion vectors for which the vector searching unit has searched, and performs motion compensation by using the areas in the decoded images and the motion vectors for which the vector searching unit has searched.
摘要翻译： 代码转换装置包括解码单元，其以第一编码格式对来自编码图像的宏块运动矢量和图像进行解码; 第一解码图像存储单元，其中存储有解码的宏块和解码图像的运动矢量; 矢量搜索单元，通过使用存储在第一解码图像存储单元中的解码图像作为参考图像并通过使用存储在第一解码图像存储单元中的解码运动矢量来搜索第二编码格式的宏块的运动矢量; 以及运动补偿单元，其从第一解码图像存储单元读取由矢量搜索单元搜索的运动矢量指示的解码图像中的区域，并且通过使用解码图像中的区域来执行运动补偿 以及向量搜索单元搜索到的运动矢量。
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9.发明授权Method for logic checking to check operation of circuit to be connected to bus 失效用于检查要连接到总线的电路运行的逻辑检查方法公开(公告)号：US07548841B2
公开(公告)日：2009-06-16
申请号：US10291508
申请日：2002-11-12
CPC分类号： G01R31/318357 , G01R31/318314 , G06F17/5022
摘要： To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.
摘要翻译： 为了检查要连接到至少一个主电路和至少一个从电路的总线的检查电路的操作，将模型连接到总线来代替主电路或从电路，并且产生给定信号 在给定的定时输出以检查要检查的电路的操作。 特别是通过多种模式的随机定时进行各种数据传送，容易引起比实际情况更严重的问题，能够提高检查效率。 例如，当检查总线仲裁器的操作时，代替多个主电路连接多个主机模型，以便在随机定时从每个主模型输出总线可访问性的请求，以检查总线的仲裁操作 仲裁者。
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