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    Semiconductor integrated circuit having fuse circuit and driving method of fuse circuit
    2.
    发明授权
    Semiconductor integrated circuit having fuse circuit and driving method of fuse circuit 失效
    具有熔丝电路和熔丝电路驱动方式的半导体集成电路

    公开(公告)号：US08508284B2

    公开(公告)日：2013-08-13

    申请号：US13337514

    申请日：2011-12-27

    Applicant: Young-Han Jeong

    Inventor： Young-Han Jeong

    IPC: H01H37/76

    CPC classification number: G11C17/16 ,  G11C17/18

    Abstract: A semiconductor integrated circuit includes a fuse connected between a first node and a second node, a first driver configured to pull down a voltage of the first node in an initialization period in response to a fuse sensing signal, a second driver configured to pull up a voltage of the second node in an initial period of a fuse sensing period in response to the fuse sensing signal, a sensor configured to determine whether the fuse is blown or not in response to a voltage of the first node, and a third driver configured to drive the second node to a voltage level lower than a pull-up voltage level of the second driver after the initial period of the fuse sensing period in response to an output signal of the sensor and the fuse sensing signal.

    Abstract translation: 半导体集成电路包括连接在第一节点和第二节点之间的熔丝，第一驱动器，被配置为在初始化时段内响应于熔丝感测信号来降低第一节点的电压;第二驱动器，被配置为将 响应于保险丝感测信号在熔丝感测周期的初始周期中的第二节点的电压;被配置为响应于第一节点的电压来确定熔丝是否被熔断的传感器，以及配置为 响应于传感器的输出信号和熔丝感测信号，在熔丝感测周期的初始周期之后，将第二节点驱动到低于第二驱动器的上拉电压电平的电压电平。

    Circuit for generating sense amplifier control signal for semiconductor memory
    4.
    发明授权
    Circuit for generating sense amplifier control signal for semiconductor memory 有权
    用于产生半导体存储器的读出放大器控制信号的电路

    公开(公告)号：US06380784B1

    公开(公告)日：2002-04-30

    申请号：US09599614

    申请日：2000-06-23

    Applicant: Young-Han Jeong

    Inventor： Young-Han Jeong

    IPC: H03H1126

    CPC classification number: H03K5/153 ,  H03K5/151

    Abstract: A circuit is provided that generates a sense amplifier control signal for a semiconductor memory in which signal paths for a normal operation and a refresh operation are separately formed so that a pulse width of an overdriving interval in the refresh operation is reduced. The reduced overdriving interval in the refresh operation reduces a refresh current. The circuit for generating the sense amplifier control signal for a semiconductor memory circuit can include a first delay that delays a sense amplifier enable signal for a first delay time, a second delay that delays an output signal from the first delay for a second delay time and a logic unit that receives output signals from the first delay and from the second delay and operates in normal operations and refresh operations in accordance with a refresh control signal to perform a logic operation on the output signals of the first and second delays, so that the overdriving interval is set shorter for the refresh operation relative to the normal operation.

    Abstract translation: 提供了一种电路，其产生用于半导体存储器的读出放大器控制信号，其中用于正常操作和刷新操作的信号路径被分开形成，使得刷新操作中的过驱动间隔的脉冲宽度减小。 刷新操作中减少的过驱动间隔减少刷新电流。 用于产生用于半导体存储器电路的读出放大器控制信号的电路可以包括第一延迟，其延迟第一延迟时间的读出放大器使能信号，延迟来自第一延迟的输出信号以延迟第二延迟时间;以及 逻辑单元，其从第一延迟和第二延迟接收输出信号，并根据刷新控制信号进行正常操作和刷新操作，以对第一和第二延迟的输出信号执行逻辑运算，从而使得 相对于正常操作，刷新操作的过驱动间隔设定得较短。

    Semiconductor memory apparatus equipped with an error control circuit for preventing coupling noise
    6.
    发明授权
    Semiconductor memory apparatus equipped with an error control circuit for preventing coupling noise 有权
    配备有用于防止耦合噪声的误差控制电路的半导体存储装置

    公开(公告)号：US08730748B2

    公开(公告)日：2014-05-20

    申请号：US13604504

    申请日：2012-09-05

    Applicant: Young Han Jeong

    Inventor： Young Han Jeong

    IPC: G11C7/02

    CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22

    Abstract: A semiconductor memory apparatus includes a plurality of memory banks, wherein each memory bank includes a bank control unit configured to reduce a voltage level of a first node to a ground voltage level when the memory bank is selected to perform a predetermined operation; an error control unit configured to supply an external voltage to the first node when the memory bank is not selected to perform the predetermined operation; and a signal generation unit configured to generate a bank operation signal in response to the voltage level of the first node.

    Abstract translation: 一种半导体存储装置，包括多个存储体，其中每个存储体包括存储体控制单元，其被配置为当存储体被选择以执行预定操作时将第一节点的电压电平降低到接地电压电平; 错误控制单元，被配置为当所述存储体未被选择以执行所述预定操作时，向所述第一节点提供外部电压; 以及信号生成单元，被配置为响应于所述第一节点的电压电平而生成存储体操作信号。

    POLYIMIDE FILM
    7.
    发明申请
    POLYIMIDE FILM 审中-公开
    聚酰亚胺膜

    公开(公告)号：US20110245455A1

    公开(公告)日：2011-10-06

    申请号：US13075849

    申请日：2011-03-30

    Applicant: Young Han JEONG ,  Hyo Jun Park ,  Hak Gee Jung

    Inventor： Young Han JEONG ,  Hyo Jun Park ,  Hak Gee Jung

    IPC: C08G73/10

    CPC classification number: C08L79/08 ,  C08G73/1039 ,  C08G73/1042

    Abstract: The present invention provides a polyimide film having a good transparency and also an excellent thermal resistance so that it is useful in a transparent conductive film, TFT substrate, a flexible printing circuit substrate, and the like.

    Abstract translation: 本发明提供了具有良好的透明性和优异的耐热性的聚酰亚胺膜，因此其可用于透明导电膜，TFT基板，柔性印刷电路基板等。

    INTEGRATED CIRCUIT
    9.
    发明申请
    INTEGRATED CIRCUIT 审中-公开
    集成电路

    公开(公告)号：US20120105139A1

    公开(公告)日：2012-05-03

    申请号：US12982731

    申请日：2010-12-30

    Applicant: Young-Han JEONG

    Inventor： Young-Han JEONG

    IPC: G05F1/10

    CPC classification number: G11C7/1057 ,  G11C7/1084 ,  G11C11/4074 ,  G11C2207/2227

    Abstract: An integrated circuit includes a first driving unit configured to drive an output terminal to a first power supply voltage in response to an active mode signal, a second driving unit configured to drive the output terminal to a second power supply voltage in response to a standby mode signal, and a current control unit configured to control the current path between the first driving unit and the first power supply voltage terminal in response to a mode control signal denoting the active mode signal and the standby mode signal.

    Abstract translation: 集成电路包括：第一驱动单元，被配置为响应于主动模式信号将输出端驱动到第一电源电压;第二驱动单元，被配置为响应于待机模式将输出端驱动到第二电源电压 信号和电流控制单元，其被配置为响应于表示有源模式信号和待机模式信号的模式控制信号来控制第一驱动单元和第一电源电压端子之间的电流路径。

    Semiconductor memory device including a fuse set and a current controlling unit
    10.
    发明授权
    Semiconductor memory device including a fuse set and a current controlling unit 失效
    半导体存储器件

    公开(公告)号：US08023354B2

    公开(公告)日：2011-09-20

    申请号：US12486784

    申请日：2009-06-18

    Applicant: Young-Han Jeong

    Inventor： Young-Han Jeong

    IPC: G11C17/18 ,  G11C7/00 ,  G11C17/00

    CPC classification number: G11C17/18 ,  G11C8/10 ,  G11C17/16 ,  G11C29/789

    Abstract: A semiconductor memory device includes a fuse set configured to form a current path including at least one of a plurality of fuses in response to address information corresponding to a plurality of memory cells and to output a redundancy address corresponding to a programming state of the plurality of fuses where the plurality of fuses are programmed with address information corresponding to a target memory cell to be repaired among the plurality of memory cells, and at least one current controlling unit configured to control a driving current flowing through the current path according to at least one detection signal.

    Abstract translation: 半导体存储器件包括：熔丝组，其被配置为响应于与多个存储单元相对应的地址信息形成包括多个保险丝中的至少一个的电流路径，并输出与多个存储单元的编程状态相对应的冗余地址 多个保险丝的编熔保险丝与在多个存储器单元中要修复的目标存储器单元相对应的地址信息，以及至少一个电流控制单元，被配置为根据至少一个控制流经电流路径的驱动电流 检测信号。

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