利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

15 条记录 (耗时 0.018 秒)

    DETECTING DEVICE AND CONVEYOR SYSTEM
    1.
    发明申请
    DETECTING DEVICE AND CONVEYOR SYSTEM 失效
    检测装置和输送机系统

    公开(公告)号：US20130161158A1

    公开(公告)日：2013-06-27

    申请号：US13532844

    申请日：2012-06-26

    申请人： ZHEN-YU MIAO ,  ZHONG-KUN XIAO

    发明人： ZHEN-YU MIAO ,  ZHONG-KUN XIAO

    IPC分类号： B65G43/10 ,  G01N37/00

    CPC分类号： H05K13/021

    摘要： A conveyor system includes a splicing belt, a supporting member, a driving module, a trigger module, a detecting module. The splicing belt is attached to the first conveyor belt and the second conveyor belt for joining the second conveyor belt to the first conveyor belt. The supporting member supports the first conveyor belt and the second conveyor belt. The driving module drives the first conveyor belt to be moved relative to the supporting member. The trigger module is located between the supporting member and the first conveyor belt, and is triggered when the splicing belt is moved to be contacted with the trigger module. The detecting module records a trigger time when the trigger module is triggered, the trigger time is a material transition time at which the first materials being fed is changed to the second materials.

    摘要翻译： 输送系统包括拼接带，支撑构件，驱动模块，触发模块，检测模块。 拼接带附接到第一输送带和第二输送带，用于将第二输送带连接到第一输送带。 支撑构件支撑第一输送带和第二输送带。 驱动模块驱动第一传送带相对于支撑构件移动。 触发模块位于支撑构件和第一输送带之间，并且当拼接带移动以与触发器模块接触时被触发。 当触发模块被触发时，检测模块记录触发时间，触发时间是将被馈送的第一材料改变为第二材料的材料转换时间。

    Level shifter circuits and methods for maintaining duty cycle
    2.
    发明授权
    Level shifter circuits and methods for maintaining duty cycle 有权
    电平移位器电路和维持占空比的方法

    公开(公告)号：US07868658B1

    公开(公告)日：2011-01-11

    申请号：US12350172

    申请日：2009-01-07

    申请人： Xiao Yu Miao

    发明人： Xiao Yu Miao

    IPC分类号： H03K19/094 ,  H03K19/0175

    CPC分类号： H03K19/018521

    摘要： A circuit comprises first and second buffers, and an output buffer. The first buffer receives an input signal and provides a first buffer output signal on a first lead. The second buffer receives the input signal and provides a second buffer output signal on a second output lead. The output buffer has a first input lead coupled to the first output lead and AC coupled to the second output lead. The AC coupling communicates timing information from the second buffer to the output buffer. The first buffer applies sufficient voltage to control the first input lead of the output buffer under DC conditions.

    摘要翻译： 电路包括第一和第二缓冲器以及输出缓冲器。 第一缓冲器接收输入信号并在第一引线上提供第一缓冲器输出信号。 第二缓冲器接收输入信号并在第二输出引线上提供第二缓冲器输出信号。 输出缓冲器具有耦合到第一输出引线的第一输入引线和耦合到第二输出引线的AC。 AC耦合将定时信息从第二缓冲器传送到输出缓冲器。 第一个缓冲器在直流条件下施加足够的电压来控制输出缓冲器的第一个输入引线。

    On-board FIFO memory module for high speed digital sourcing and capture to/from DUT (device under test) using a clock from DUT
    3.
    发明授权
    On-board FIFO memory module for high speed digital sourcing and capture to/from DUT (device under test) using a clock from DUT 有权
    板载FIFO存储器模块，用于使用DUT的时钟进行高速数字采集和捕获到DUT（被测器件）

    公开(公告)号：US07640471B2

    公开(公告)日：2009-12-29

    申请号：US11580761

    申请日：2006-10-13

    申请人： Yu Miao ,  Elizabeth Vigrass ,  Shawn C. Smith

    发明人： Yu Miao ,  Elizabeth Vigrass ,  Shawn C. Smith

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31926 ,  G01R31/31922

    摘要： In a method and system for testing, a tester (110) is operable to communicate test signals (124, 126) at a tester clock speed, and a device (190) to be tested is operable to communicate the test signals (124, 126) at a device clock speed, the device clock speed being greater than the tester clock speed. A test module (120) is interposed between the tester (110) and the device (190) to enable data transfer between the tester (110) and the device (190) at their respective clock speeds. The test module (120) includes a memory module (250) capable of storing N samples of the test signals (124, 126) at a selectable one of the tester clock speed and the device clock speed. The memory module (250) is operable to provide the N samples at a selectable one of the tester clock speed and the device clock speed.

    摘要翻译： 在用于测试的方法和系统中，测试器（110）可操作以以测试器时钟速度传送测试信号（124,126），并且待测试的设备（190）可操作以传送测试信号（124,126 ），器件时钟速度大于测试仪时钟速度。 测试模块（120）插入在测试器（110）和设备（190）之间，以使得能够以它们各自的时钟速度在测试器（110）和设备（190）之间进行数据传输。 测试模块（120）包括能够以测试器时钟速度和设备时钟速度的可选择的一个存储测试信号（124,126）的N个采样的存储器模块（250）。 存储器模块（250）可操作以以测试仪时钟速度和设备时钟速度的可选择的一个提供N个采样。

    Detecting device and conveyor system
    5.
    发明授权
    Detecting device and conveyor system 失效
    检测装置和输送机系统

    公开(公告)号：US08602206B2

    公开(公告)日：2013-12-10

    申请号：US13532844

    申请日：2012-06-26

    申请人： Zhen-Yu Miao ,  Zhong-Kun Xiao

    发明人： Zhen-Yu Miao ,  Zhong-Kun Xiao

    IPC分类号： B65G43/10 ,  B65G43/08

    CPC分类号： H05K13/021

    摘要： A conveyor system includes a splicing belt, a supporting member, a driving module, a trigger module, a detecting module. The splicing belt is attached to the first conveyor belt and the second conveyor belt for joining the second conveyor belt to the first conveyor belt. The supporting member supports the first conveyor belt and the second conveyor belt. The driving module drives the first conveyor belt to be moved relative to the supporting member. The trigger module is located between the supporting member and the first conveyor belt, and is triggered when the splicing belt is moved to be contacted with the trigger module. The detecting module records a trigger time when the trigger module is triggered, the trigger time is a material transition time at which the first materials being fed is changed to the second materials.

    摘要翻译： 输送系统包括拼接带，支撑构件，驱动模块，触发模块，检测模块。 拼接带附接到第一输送带和第二输送带，用于将第二输送带连接到第一输送带。 支撑构件支撑第一输送带和第二输送带。 驱动模块驱动第一传送带相对于支撑构件移动。 触发模块位于支撑构件和第一输送带之间，并且当拼接带移动以与触发器模块接触时被触发。 当触发模块被触发时，检测模块记录触发时间，触发时间是将被馈送的第一材料改变为第二材料的材料转换时间。

    Low power preamplifier writer architecture
    7.
    发明授权
    Low power preamplifier writer architecture 有权
    低功率前置放大器写入器架构

    公开(公告)号：US07408313B1

    公开(公告)日：2008-08-05

    申请号：US11321766

    申请日：2005-12-28

    申请人： Chan Sang Kong ,  Kien Beng Tan ,  Xiao Yu Miao

    发明人： Chan Sang Kong ,  Kien Beng Tan ,  Xiao Yu Miao

    IPC分类号： H02P3/00 ,  H03K3/00

    CPC分类号： G11B5/09 ,  G11B5/022

    摘要： A circuit is adapted to activate a writer head of a data storage media drive during both the boost periods as well as the steady state periods. The current supplied to the writer head during the boost periods exceeds the steady state current and flows between positive and negative voltage supplies so as to provide the required magnetic flux change in the inductor disposed in the write head. During the steady state periods, a switch circuit is turned on to provide a second current path across the writer head. During the steady state periods, the current flows between the positive voltage supply and the ground to reduce power consumption. The switch circuit is turned off during the boost periods.

    摘要翻译： 电路适于在升压期间和稳定状态期间激活数据存储介质驱动器的写入头。 在升压期间提供给写入头的电流超过稳态电流，并且在正和负电压源之间流动，以便在设置在写入头中的电感器中提供所需的磁通量变化。 在稳定状态期间，开关电路导通以提供穿过写入头的第二电流路径。 在稳态期间，电流在正电源和地之间流动，以降低功耗。 开关电路在升压期间关闭。