公开(公告)号：US06767837B2

公开(公告)日：2004-07-27

申请号：US10379969

申请日：2003-03-05

申请人： Yu-Chi Sun ,  Tse-Yao Huang

发明人： Yu-Chi Sun ,  Tse-Yao Huang

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/31055

摘要： A method of inter-layer dielectric (ILD) or inter-metal dielectric (IMD) planarization. Reactive ion etching (RIE) is performed with gases including equal amounts of C5F8 and CHF3, and argon diluent gas. The ratio of the gas is precisely controlled in the etching, and once the oxygen concentration drops, the etching process enters deposition of the protection layer, and when oxygen concentration drops to a minimum level, the etch-back process stops automatically. Higher ILD or IMD uniformity is achieved compared with conventional CMP process.

公开(公告)号：US06759300B2

公开(公告)日：2004-07-06

申请号：US10424526

申请日：2003-04-28

申请人： Chao-Wen Lay ,  Yu-Chi Sun ,  Tse-Yao Huang

发明人： Chao-Wen Lay ,  Yu-Chi Sun ,  Tse-Yao Huang

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/42324

摘要： A method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conductive layer, a first insulating layer, and a patterned mask layer with an opening are formed, such that the opening exposes the first insulating layer. The insulating layer and the conducting layer are sequentially etched to form a round-cornered trench, and the photo hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are removed using the second insulating layer as a mask, and the first conducting layer covered by the second insulating layer remains as a floating gate.

摘要翻译： 一种用于制造浮动栅极的方法。 提供半导体衬底，其上形成有栅极电介质层，导电层，第一绝缘层和具有开口的图案化掩模层，使得开口暴露第一绝缘层。 依次蚀刻绝缘层和导电层以形成圆角沟槽，并去除光硬掩模层。 在圆角沟槽中形成第二绝缘层。 使用第二绝缘层作为掩模去除第一绝缘层和暴露的导电层，并且由第二绝缘层覆盖的第一导电层保持为浮栅。

公开(公告)号：US06680254B2

公开(公告)日：2004-01-20

申请号：US09939110

申请日：2001-08-24

申请人： Yu-Chi Sun ,  Tse-Yao Huang

发明人： Yu-Chi Sun ,  Tse-Yao Huang

IPC分类号： H01L21311

CPC分类号： H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell fabrication avoiding bit line encroaching. A first insulating layer and a first masking layer are formed on a semiconductor substrate with a diffused region. The first masking layer and the first insulating layer are defined to form a first trench above the diffusion region. A second masking layer is formed to fill the first trench, and a hole is formed by removing a portion of the second masking layer above the diffusion region. A bit line contact is formed by removing a portion of the first insulating layer beneath the hole to expose the diffusion region. A bit line contact plug is formed by filling the bit line contact with a first conductive layer. The residual second masking layer and the first masking layer are removed to form a second trench. A bit line is formed by filling the second trench with a second conductive layer.

摘要翻译： 一种避免位线侵占的存储单元制造。 在具有扩散区域的半导体衬底上形成第一绝缘层和第一掩蔽层。 第一掩模层和第一绝缘层被限定以形成扩散区上方的第一沟槽。 形成第二掩模层以填充第一沟槽，并且通过去除扩散区域上方的第二掩蔽层的一部分来形成孔。 通过去除孔下面的第一绝缘层的一部分以暴露扩散区域来形成位线接触。 通过将位线接触填充到第一导电层来形成位线接触插塞。 去除残留的第二掩模层和第一掩模层以形成第二沟槽。 通过用第二导电层填充第二沟槽来形成位线。

公开(公告)号：US06586324B2

公开(公告)日：2003-07-01

申请号：US10057085

申请日：2002-01-25

申请人： Tse-Yao Huang ,  Chih-Ching Lin ,  Yu-Chi Sun ,  Chang Rong Wu ,  Shing-Yih Shih

发明人： Tse-Yao Huang ,  Chih-Ching Lin ,  Yu-Chi Sun ,  Chang Rong Wu ,  Shing-Yih Shih

IPC分类号： H01L214763

CPC分类号： H01L21/76837 ,  H01L21/76834

摘要： A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.

摘要翻译： 形成互连的方法。 形成具有图案的氧化物掩模层，覆盖金属层。 将掩模层的图案转移到金属层中以形成开口。 然后，在掩模层，金属层和第一绝缘层上共形地形成氮化硅衬垫。 接下来，通过反应离子蚀刻部分去除氮化硅衬垫和掩模层以留下刻面掩模以减小开口的纵横比，随后除去剩余的氮化硅衬垫。 然后，沉积绝缘层以填充开口。