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公开(公告)号:US08037322B2
公开(公告)日:2011-10-11
申请号:US12037621
申请日:2008-02-26
申请人: Ryoichiro Yamanaka , Yuji Fukuoka
发明人: Ryoichiro Yamanaka , Yuji Fukuoka
CPC分类号: G06F1/3203 , G06F1/3275 , G06F1/3287 , Y02D10/14 , Y02D10/171
摘要: A power reducer for data backup stops a power supply one after another for each memory whose backup has been completed, thereby reducing power consumption for battery during the backup lengthening a data backup time. The power reducer for data backup in a device includes an external power supply unit supplying power to the device, auxiliary power supply unit charging based upon the power supply from the external power supply unit and supplying auxiliary power to the device when the power from the external power supply unit is stopped, a cache memory having first and second memory units and recording a part of data stored in a storage medium, and a controller controlling power from the auxiliary power supply unit to the device and stopping power to the first or second memory unit one after another.
摘要翻译: 用于数据备份的减速器为备份完成的每个存储器依次停止电源,从而在备份期间延长电池的功耗,延长数据备份时间。 用于设备中的数据备份的功率减小器包括:向设备供电的外部电源单元,辅助电源单元根据来自外部电源单元的电源进行充电,并且当来自外部电源的电力时向辅助电源供应辅助电力 电源单元停止,具有第一和第二存储器单元并且记录存储在存储介质中的一部分数据的高速缓冲存储器,以及控制从辅助电源单元向设备供电的控制器并且停止向第一或第二存储器供电的控制器 单位一个接一个
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公开(公告)号:US20080229133A1
公开(公告)日:2008-09-18
申请号:US12037621
申请日:2008-02-26
申请人: Ryoichiro YAMANAKA , Yuji Fukuoka
发明人: Ryoichiro YAMANAKA , Yuji Fukuoka
IPC分类号: G06F1/32
CPC分类号: G06F1/3203 , G06F1/3275 , G06F1/3287 , Y02D10/14 , Y02D10/171
摘要: A power reducer for data backup stops a power supply one after another for each memory whose backup has been completed, thereby reducing power consumption for battery during the backup lengthening a data backup time. The power reducer for data backup in a device includes an external power supply unit supplying power to the device, auxiliary power supply unit charging based upon the power supply from the external power supply unit and supplying auxiliary power to the device when the power from the external power supply unit is stopped, a cache memory having first and second memory units and recording a part of data stored in a storage medium, and a controller controlling power from the auxiliary power supply unit to the device and stopping power to the first or second memory unit one after another.
摘要翻译: 用于数据备份的减速器为备份完成的每个存储器依次停止电源,从而在备份期间延长电池的功耗,延长数据备份时间。 用于设备中的数据备份的功率减小器包括:向设备供电的外部电源单元,辅助电源单元根据来自外部电源单元的电源进行充电,并且当来自外部电源的电力时向辅助电源供应辅助电力 电源单元停止,具有第一和第二存储器单元并且记录存储在存储介质中的一部分数据的高速缓冲存储器,以及控制从辅助电源单元向设备供电的控制器并且停止向第一或第二存储器供电的控制器 单位一个接一个
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公开(公告)号:US09722075B2
公开(公告)日:2017-08-01
申请号:US15106918
申请日:2014-10-16
申请人: Akitaka Soeno , Yuji Fukuoka
发明人: Akitaka Soeno , Yuji Fukuoka
IPC分类号: H01L29/78 , H01L29/66 , H01L29/739 , H01L29/06
CPC分类号: H01L29/7827 , H01L29/0634 , H01L29/0661 , H01L29/66666 , H01L29/7397 , H01L29/78
摘要: Described herein is a semiconductor device including a semiconductor substrate in which an element region and a termination region surrounding the element region are provided. The element region includes: a gate trench; a gate insulating film; and a gate electrode. The termination region includes: a plurality of termination trenches provided around the element region; an inner trench insulating layer located inside of each of the plurality of termination trenches; and an upper surface insulating layer located at an upper surface of the semiconductor substrate in the termination region. The upper surface insulating layer includes a first portion and a second portion having a thinner thickness than the first portion and located at a location separated from the element region than the first portion, and a gate wiring is located at an upper surface of the first portion and is not located at an upper surface of the second portion.
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公开(公告)号:US20170040448A1
公开(公告)日:2017-02-09
申请号:US15106918
申请日:2014-10-16
申请人: Akitaka SOENO , Yuji FUKUOKA
发明人: Akitaka SOENO , Yuji FUKUOKA
CPC分类号: H01L29/7827 , H01L29/0634 , H01L29/0661 , H01L29/66666 , H01L29/7397 , H01L29/78
摘要: Described herein is a semiconductor device including a semiconductor substrate in which an element region and a termination region surrounding the element region are provided. The element region includes: a gate trench; a gate insulating film; and a gate electrode. The termination region includes: a plurality of termination trenches provided around the element region; an inner trench insulating layer located inside of each of the plurality of termination trenches; and an upper surface insulating layer located at an upper surface of the semiconductor substrate in the termination region. The upper surface insulating layer includes a first portion and a second portion having a thinner thickness than the first portion and located at a location separated from the element region than the first portion, and a gate wiring is located at an upper surface of the first portion and is not located at an upper surface of the second portion.
摘要翻译: 这里描述的是包括半导体衬底的半导体器件,其中设置元件区域和围绕元件区域的端接区域。 元件区域包括:栅极沟槽; 栅极绝缘膜; 和栅电极。 终端区域包括:设置在元件区域周围的多个终端沟槽; 位于所述多个终端沟槽的每一个内部的内部沟槽绝缘层; 以及位于终端区域中的半导体衬底的上表面处的上表面绝缘层。 所述上表面绝缘层包括第一部分和第二部分,所述第一部分和第二部分具有比所述第一部分更薄的厚度,并且位于与所述第一部分相比元件区域分离的位置处,并且栅极布线位于所述第一部分的上表面 并且不位于第二部分的上表面。
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