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公开(公告)号：US20210311737A1
公开(公告)日：2021-10-07
申请号：US17324563
申请日：2021-05-19
发明人： Gregory W. Smaus , Francesco Spadini , Matthew A. Rafacz , Michael Achenbach , Christopher J. Burke , Emil Talpes , Matthew M. Crum
摘要： An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.
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公开(公告)号：US20140181482A1
公开(公告)日：2014-06-26
申请号：US13723103
申请日：2012-12-20
发明人： Gregory W. Smaus , Francesco Spadini , Matthew A. Rafacz , Michael Achenbach , Christopher J. Burke , Emil Talpes , Matthew M. Crum
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/3826 , G06F9/384
摘要： An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.
摘要翻译： 算术单元根据存储指令和加载指令之间的预测依赖关系执行存储到载入转发。 在一些实施例中，算术单元保持正在等待移动到指令流水线的加载/存储单元的存储指令表。 响应于接收到被预测为依赖于存储在表中的存储指令的加载指令，运算单元使与存储指令相关联的数据被放入由加载指令所针对的物理寄存器中。 在一些实施例中，算术单元通过将由加载指令指定的物理寄存器映射到与存储指令相关联的数据所位于的物理寄存器来执行转发。
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公开(公告)号：US09606806B2
公开(公告)日：2017-03-28
申请号：US13926184
申请日：2013-06-25
CPC分类号： G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3863
摘要： A method includes selecting for execution in a processor a load instruction having at least one dependent instruction. Responsive to selecting the load instruction, the at least one dependent instruction is selectively awakened based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution. A processor includes an instruction pipeline having an execution unit to execute instructions, a scheduler, and a controller. The scheduler selects for execution in the execution unit a load instruction having at least one dependent instruction. The controller, responsive to the scheduler selecting the load instruction, selectively awakens the at least one dependent instruction based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution by the execution unit.
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4.发明公开公开(公告)号：US20240004665A1
公开(公告)日：2024-01-04
申请号：US17855528
申请日：2022-06-30
IPC分类号： G06F9/22
CPC分类号： G06F9/223
摘要： A disclosed method for making efficient picks of micro-operations for execution includes selecting a first set of micro-operations that are ready for execution during a certain clock cycle. The method also includes selecting a second set of micro-operations that are ready for execution during the certain clock cycle. The method additionally includes replacing one or more of the complex micro-operations included in the first set of micro-operations with one or more simple micro-operations included in the second set of micro-operations due at least in part to a number of complex micro-operations included in the first set of micro-operations exceeding a set of complex resources capable of executing the complex micro-operations. Various other apparatuses, systems, and methods are also disclosed.
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公开(公告)号：US11379234B2
公开(公告)日：2022-07-05
申请号：US17324563
申请日：2021-05-19
发明人： Gregory W. Smaus , Francesco Spadini , Matthew A. Rafacz , Michael Achenbach , Christopher J. Burke , Emil Talpes , Matthew M. Crum
摘要： An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.
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公开(公告)号：US11036505B2
公开(公告)日：2021-06-15
申请号：US13723103
申请日：2012-12-20
发明人： Gregory W. Smaus , Francesco Spadini , Matthew A. Rafacz , Michael Achenbach , Christopher J. Burke , Emil Talpes , Matthew M. Crum
摘要： An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.
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