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公开(公告)号：US09003225B2
公开(公告)日：2015-04-07
申请号：US13653924
申请日：2012-10-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Matthew A. Rafacz , Matthew M. Crum , Michael E. Tuuk
CPC classification number: G06F11/0721 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F11/0751
Abstract: A processor includes a store queue that stores information representing store instructions. In response to retirement of a store instruction, the processor invalidates the corresponding entry in the store queue, thereby indicating that the entry is available to store a subsequent store instruction. The store address is not removed from the queue until the subsequent store instruction is stored. Accordingly, the store address is available for comparison to a dependent load address.
Abstract translation: 处理器包括存储表示存储指令的信息的存储队列。 响应于存储指令的退出，处理器使存储队列中的相应条目无效，从而指示该条目可用于存储后续存储指令。 存储地址不会从队列中删除，直到存储后续存储指令。 因此，存储地址可用于与依赖负载地址进行比较。
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公开(公告)号：US11868818B2
公开(公告)日：2024-01-09
申请号：US15273304
申请日：2016-09-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Gregory W. Smaus , John M. King , Matthew A. Rafacz , Matthew M. Crum
Abstract: Techniques for selectively executing a lock instruction speculatively or non-speculatively based on lock address prediction and/or temporal lock prediction. including methods an devices for locking an entry in a memory device. In some techniques, a lock instruction executed by a thread for a particular memory entry of a memory device is detected. Whether contention occurred for the particular memory entry during an earlier speculative lock is detected on a condition that the lock instruction comprises a speculative lock instruction. The lock is executed non-speculatively if contention occurred for the particular memory entry during an earlier speculative lock. The lock is executed speculatively if contention did not occur for the particular memory entry during an earlier speculative lock.
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公开(公告)号：US20220091653A1
公开(公告)日：2022-03-24
申请号：US17030324
申请日：2020-09-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Mahesh Subramony , David Suggs , Michael T. Clark , Matthew M. Crum
IPC: G06F1/3206 , G06F1/28 , G06F1/3287
Abstract: A method of operating a processing unit includes, in response to detecting that the processing unit is operating in a voltage limited state, calculating a set of headroom values by calculating a headroom value for each operational constraint in a set of operational constraints of the processing unit, based on the calculated set of headroom values, selecting from a set of performance features a subset of one or more performance features for enabling in the processing unit, and enabling the selected subset of performance features in the processing unit.
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公开(公告)号：US11379234B2
公开(公告)日：2022-07-05
申请号：US17324563
申请日：2021-05-19
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Gregory W. Smaus , Francesco Spadini , Matthew A. Rafacz , Michael Achenbach , Christopher J. Burke , Emil Talpes , Matthew M. Crum
Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.
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公开(公告)号：US11036505B2
公开(公告)日：2021-06-15
申请号：US13723103
申请日：2012-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Gregory W. Smaus , Francesco Spadini , Matthew A. Rafacz , Michael Achenbach , Christopher J. Burke , Emil Talpes , Matthew M. Crum
Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.
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Patent Agency Ranking
公开(公告)号：US20180081544A1
公开(公告)日：2018-03-22
申请号：US15273304
申请日：2016-09-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Gregory W. Smaus , John M. King , Matthew A. Rafacz , Matthew M. Crum
IPC: G06F3/06 , G06F12/084 , G06F12/0842
Abstract: Techniques for selectively executing a lock instruction speculatively or non-speculatively based on lock address prediction and/or temporal lock prediction. including methods an devices for locking an entry in a memory device. In some techniques, a lock instruction executed by a thread for a particular memory entry of a memory device is detected. Whether contention occurred for the particular memory entry during an earlier speculative lock is detected on a condition that the lock instruction comprises a speculative lock instruction. The lock is executed non-speculatively if contention occurred for the particular memory entry during an earlier speculative lock. The lock is executed speculatively if contention did not occur for the particular memory entry during an earlier speculative lock.
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公开(公告)号：US20210311737A1
公开(公告)日：2021-10-07
申请号：US17324563
申请日：2021-05-19
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Gregory W. Smaus , Francesco Spadini , Matthew A. Rafacz , Michael Achenbach , Christopher J. Burke , Emil Talpes , Matthew M. Crum
Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.
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公开(公告)号：US20140181482A1
公开(公告)日：2014-06-26
申请号：US13723103
申请日：2012-12-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Gregory W. Smaus , Francesco Spadini , Matthew A. Rafacz , Michael Achenbach , Christopher J. Burke , Emil Talpes , Matthew M. Crum
IPC: G06F9/30
CPC classification number: G06F9/30043 , G06F9/3826 , G06F9/384
Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.
Abstract translation: 算术单元根据存储指令和加载指令之间的预测依赖关系执行存储到载入转发。 在一些实施例中，算术单元保持正在等待移动到指令流水线的加载/存储单元的存储指令表。 响应于接收到被预测为依赖于存储在表中的存储指令的加载指令，运算单元使与存储指令相关联的数据被放入由加载指令所针对的物理寄存器中。 在一些实施例中，算术单元通过将由加载指令指定的物理寄存器映射到与存储指令相关联的数据所位于的物理寄存器来执行转发。
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公开(公告)号：US20140181407A1
公开(公告)日：2014-06-26
申请号：US13726825
申请日：2012-12-26
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Matthew M. Crum , Teik-Chung Tan
IPC: G06F12/08
CPC classification number: G06F12/0895 , G06F1/3275 , Y02D10/13 , Y02D10/14
Abstract: For a memory access at a processor, only a subset (less than all) of the ways of a cache associated with a memory address is prepared for access. The subset of ways is selected based on stored information indicating, for each memory access, which corresponding way of the cache was accessed. The subset of ways is selected and preparation of the subset of ways is initiated prior to the final determination as to which individual cache way in the subset is to be accessed.
Abstract translation: 对于在处理器处的存储器访问，仅准备存储器与存储器地址相关联的高速缓存的一个子集（少于全部）以进行访问。 基于存储的信息来选择方法的子集，该信息指示对于每个存储器访问，哪个高速缓存的相应方式被访问。 选择方法的子集，并且在最终确定要在子集中访问哪个单独缓存方式之前启动方法子集的准备。
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公开(公告)号：US20140108862A1
公开(公告)日：2014-04-17
申请号：US13653924
申请日：2012-10-17
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Matthew A. Rafacz , Matthew M. Crum , Michael E. Tuuk
CPC classification number: G06F11/0721 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F11/0751
Abstract: A processor includes a store queue that stores information representing store instructions. In response to retirement of a store instruction, the processor invalidates the corresponding entry in the store queue, thereby indicating that the entry is available to store a subsequent store instruction. The store address is not removed from the queue until the subsequent store instruction is stored. Accordingly, the store address is available for comparison to a dependent load address.
Abstract translation: 处理器包括存储表示存储指令的信息的存储队列。 响应于存储指令的退出，处理器使存储队列中的相应条目无效，从而指示该条目可用于存储后续存储指令。 存储地址不会从队列中删除，直到存储后续存储指令。 因此，存储地址可用于与依赖负载地址进行比较。
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