公开(公告)号：US20210406092A1

公开(公告)日：2021-12-30

申请号：US16945519

申请日：2020-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Leonardo DE PAULA ROSA PIGA ,  Karthik RAO ,  Indrani PAUL ,  Mahesh SUBRAMONY ,  Kenneth MITCHELL ,  Dana Glenn LEWIS ,  Sriram SAMBAMURTHY ,  Wonje CHOI

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/30

Abstract: A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.

公开(公告)号：US20220317757A1

公开(公告)日：2022-10-06

申请号：US17219097

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik RAO ,  Indrani PAUL ,  Donny YI ,  Oleksandr KHODORKOVSKY ,  Leonardo DE PAULA ROSA PIGA ,  Wonje CHOI ,  Dana G. LEWIS ,  Sriram SAMBAMURTHY

IPC: G06F1/3287 ,  G06N5/04

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

公开(公告)号：US20210182066A1

公开(公告)日：2021-06-17

申请号：US16712891

申请日：2019-12-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sukesh SHENOY ,  Adam N. C. CLARK ,  Indrani PAUL

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38 ,  G06F1/3203

Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.