公开(公告)号：US12088296B2

公开(公告)日：2024-09-10

申请号：US17554722

申请日：2021-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ramon A. Mangaser ,  Srikanth Reddy Gruddanti ,  Prasant Kumar Vallur ,  Krishna Reddy Mudimela Venkata ,  Oikwan Tsang

IPC: H03K19/20 ,  G06F1/06 ,  H03K3/037

CPC classification number: H03K19/20 ,  G06F1/06 ,  H03K3/037

Abstract: A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.