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公开(公告)号:US12088296B2
公开(公告)日:2024-09-10
申请号:US17554722
申请日:2021-12-17
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Ramon A. Mangaser , Srikanth Reddy Gruddanti , Prasant Kumar Vallur , Krishna Reddy Mudimela Venkata , Oikwan Tsang
Abstract: A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.
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公开(公告)号:US12015412B1
公开(公告)日:2024-06-18
申请号:US18060857
申请日:2022-12-01
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Srikanth Reddy Gruddanti , Pradeep Jayaraman , Ramon A. Mangaser , Prasant Kumar Vallur , Krishna Reddy Mudimela Venkata , David H. McIntyre
CPC classification number: H03K5/249 , H03K5/14 , H03L7/0998 , H03K2005/00286
Abstract: A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.
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公开(公告)号:US11960435B2
公开(公告)日:2024-04-16
申请号:US17692147
申请日:2022-03-10
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Pradeep Jayaraman , Dean Gonzales , Gerald R. Talbot , Ramon A. Mangaser , Michael J. Tresidder , Prasant Kumar Vallur , Srikanth Reddy Gruddanti , Krishna Reddy Mudimela Venkata , David H. McIntyre
IPC: G06F13/42 , H01L25/065
CPC classification number: G06F13/4291 , G06F13/4286 , H01L25/0652
Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.
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