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    Cross field effect transistor library cell architecture design
    2.
    发明授权
    Cross field effect transistor library cell architecture design 有权

    公开(公告)号：US11881393B2

    公开(公告)日：2024-01-23

    申请号：US17489316

    申请日：2021-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz

    IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L27/092

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0673

    Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.

    CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN
    3.
    发明申请
    CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN 有权

    公开(公告)号：US20230096037A1

    公开(公告)日：2023-03-30

    申请号：US17489316

    申请日：2021-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz

    IPC: H01L27/12 ,  H01L21/84

    Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.

    Gate contact over active region in cell
    5.
    发明授权
    Gate contact over active region in cell 有权

    公开(公告)号：US10818762B2

    公开(公告)日：2020-10-27

    申请号：US15989604

    申请日：2018-05-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz

    IPC: H01L21/00 ,  H01L29/423 ,  H01L21/768 ,  H01L23/535 ,  H01L27/02 ,  H01L29/66 ,  H01L29/786

    Abstract: A system and method for laying out power grid connections for standard cells are described. In various implementations, gate metal is placed over non-planar vertical conducting structures, which are used to form non-planar devices (transistors). Gate contacts connect gate metal to gate extension metal (GEM) above the gate metal. GEM is placed above the gate metal and makes a connection with gate metal through the one or more gate contacts. Gate extension contacts are formed on the GEM above the active regions. Similar to gate contacts, gate extension contacts are formed with a less complex fabrication process than using a self-aligned contacts process. Gate extension contacts connect GEM to an interconnect layer such as a metal zero layer. Gate extension contacts are aligned vertically with one of the non-planar vertical conducting structures. Therefore, in an implementation, one or more gate extension contacts are located above the active region.

    Standard cell and power grid architectures with EUV lithography
    6.
    发明授权
    Standard cell and power grid architectures with EUV lithography 有权

    公开(公告)号：US10796061B1

    公开(公告)日：2020-10-06

    申请号：US16555865

    申请日：2019-08-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz

    IPC: G06F30/394 ,  H01L27/02 ,  G06F30/392

    Abstract: A system and method for creating chip layout are described. In various embodiments, a standard cell uses unidirectional tracks for power connections and signal routing. At least two tracks of the metal one layer using a minimum width of the metal one layer are placed within a pitch of a single metal gate to provide a standard cell with a two to one “gear ratio” or greater. A power signal and a ground reference signal in the metal one layer are routed in a same metal one track to provide area for other signal routing. Multiple standard cells are placed in a multi-cell layout with routes in one or more of the metal two layer and the metal three layer using minimum lengths for power connections. The layout includes no power grid with a fixed pitch.

    Sinusoidal shaped capacitor architecture in oxide
    7.
    发明授权
    Sinusoidal shaped capacitor architecture in oxide 有权

    公开(公告)号：US10756164B2

    公开(公告)日：2020-08-25

    申请号：US15474043

    申请日：2017-03-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz

    IPC: H01L21/311 ,  H01L49/02 ,  H01L21/027 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L27/07 ,  H01L27/06 ,  H01L27/08

    Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.

    POWER GRID ARCHITECTURE AND OPTIMIZATION WITH EUV LITHOGRAPHY
    8.
    发明申请
    POWER GRID ARCHITECTURE AND OPTIMIZATION WITH EUV LITHOGRAPHY 审中-公开

    公开(公告)号：US20180314785A1

    公开(公告)日：2018-11-01

    申请号：US15636278

    申请日：2017-06-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz

    IPC: G06F17/50 ,  H01L27/02

    Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell uses unidirectional tracks for each of the multiple power vertical metal 3 layer tracks and power horizontal metal 2 tracks. One or more of the multiple vertical metal 3 layer posts are routed with a minimum length based on a pitch of power horizontal metal 2 layer straps. One or more vertical metal 1 posts used for a power connection or a ground connection are routed from a top to a bottom of an active region permitting multiple locations to be used for connections to one of the multiple power horizontal metal 2 layer straps. Two or more power horizontal metal 2 layer straps are placed within a power metal 2 layer track without being connected to one another.

    BACKSIDE POWER DELIVERY AND POWER GRID PATTERN TO SUPPORT 3D DIE STACKING
    9.
    发明公开
    BACKSIDE POWER DELIVERY AND POWER GRID PATTERN TO SUPPORT 3D DIE STACKING 审中-公开

    公开(公告)号：US20240105675A1

    公开(公告)日：2024-03-28

    申请号：US17936167

    申请日：2022-09-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz ,  John J. Wuu

    IPC: H01L25/065 ,  H01L23/48 ,  H01L23/528 ,  H01L23/538

    CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/5386

    Abstract: An apparatus and method for efficiently routing power signals across semiconductor dies. A semiconductor fabrication process (or process) places a first semiconductor die in an integrated circuit and stacks a second semiconductor die vertically adjacent to the first semiconductor die. The process forms multiple backside metal layers vertically adjacent to a backside of a silicon substrate of the second semiconductor die. The process forms a first backside metal layer that includes at least a first power route that forms a rectangle within the first backside metal layer. The process forms a second backside metal layer that includes at least a second power rail that forms an L-shape within the second backside metal layer. The process connects one or more corners of the rectangle of the first power rail to a corresponding corner of a separate power rail of the second backside metal layer that forms an L-shape.

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