公开(公告)号：US20230205696A1

公开(公告)日：2023-06-29

申请号：US17563869

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： JIMSHED MIRZA ,  MARK FOWLER

IPC: G06F12/084 ,  G06F12/0895 ,  G06F12/0811 ,  G06F9/30

CPC classification number: G06F12/084 ,  G06F12/0895 ,  G06F12/0811 ,  G06F9/3009

Abstract: Cascading execution of atomic operations, including: receiving a request for each thread of a plurality of threads to perform an atomic operation, wherein the plurality of threads comprises a plurality of thread subsets each corresponding to a local memory, wherein the local memory for a thread subset is accessible by the thread subset and inaccessible to a remainder of threads in the plurality of threads; generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.

公开(公告)号：US20230206380A1

公开(公告)日：2023-06-29

申请号：US17564138

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： ANTHONY HC CHAN ,  CHRISTOPHER J. BRENNAN ,  MARK FOWLER ,  DAVID CHUI ,  LEON K.N. LAI ,  JIMSHED MIRZA

IPC: G06T1/20 ,  G06T7/10 ,  G06T7/90

CPC classification number: G06T1/20 ,  G06T7/10 ,  G06T7/90

Abstract: A processor for optimizing partial writes to compressed blocks is configured to identify that a write request targets less than an entirety of a compressed block of pixel data, identify, based on a compression key, a compressed segment of the compressed block of pixel data that includes a target of the write request, and decompress, responsive to the write request, only the identified compressed segment of the compressed block of pixel data.

公开(公告)号：US20240111681A1

公开(公告)日：2024-04-04

申请号：US17955888

申请日：2022-09-29

Applicant: ATI TECHNOLOGIES ULC

Inventor： JIMSHED MIRZA

IPC: G06F12/0877

CPC classification number: G06F12/0877 ,  G06F2212/60

Abstract: A processor for implementing a last use cache policy is configured to access data in a portion of a cache, determine that the data in the portion of the cache is no longer needed, and mark the data in the portion of the cache as non-dirty responsive to the determining that the data in the portion of the cache is no longer needed. The marking of the data as non-dirty is indicative that the data in the portion of the cache is not to be evicted from the cache to a memory.