公开(公告)号：US20200310052A1

公开(公告)日：2020-10-01

申请号：US16642336

申请日：2018-09-03

Applicant: Agency for Science, Technology and Research

Inventor： Teck Guan Lim ,  Surya Bhattacharya

IPC: G02B6/42 ,  H01L25/16 ,  H01L23/00

Abstract: Various embodiments may relate to a method of forming a photonic integrated circuit package (PIC). The method may include forming a redistribution layer (RDL) over a carrier. The method may also include forming a through hole or cavity on the redistribution layer. The method may additionally include providing a stop-ring structure, the stop-ring structure including a ring of suitable material, the stop-ring structure defining a hollow space, over the redistribution layer so that the hollow space is over the through hole or cavity. The method may further include arranging a photonic integrated circuit (PIC) die over the redistribution layer so that the photonic integrated circuit (PIC) die is on the stop-ring structure. The method may also include forming a molded package by forming a mold structure to at least partially cover the photonic integrated circuit (PIC) die to form the photonic integrated circuit package.

公开(公告)号：US10755993B2

公开(公告)日：2020-08-25

申请号：US16084554

申请日：2017-03-16

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： David Ho ,  Vempati Srinivasa Rao ,  Tai Chong Chai ,  Surya Bhattacharya

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

Abstract: Various embodiments may provide an electrical connection structure. The electrical connection structure may include a first substrate having a first surface defining a cavity, and an inner wall defining a via extending from the cavity. The electrical connection structure may also include an interconnect structure provided in the via so that at least a portion of the interconnect structure protrudes into the cavity. The electrical connection structure may further include a second substrate having a second surface facing the first surface. The electrical connection structure may additionally include a connection element on the second surface. At least a portion of the connection element may be received in the cavity so that the connection element is in electrical connection with the interconnect structure.

公开(公告)号：US10989887B2

公开(公告)日：2021-04-27

申请号：US16642336

申请日：2018-09-03

Applicant: Agency for Science, Technology and Research

Inventor： Teck Guan Lim ,  Surya Bhattacharya

IPC: G02B6/12 ,  G02B6/42 ,  H01L23/00 ,  H01L25/16

Abstract: Various embodiments may relate to a method of forming a photonic integrated circuit package (PIC). The method may include forming a redistribution layer (RDL) over a carrier. The method may also include forming a through hole or cavity on the redistribution layer. The method may additionally include providing a stop-ring structure, the stop-ring structure including a ring of suitable material, the stop-ring structure defining a hollow space, over the redistribution layer so that the hollow space is over the through hole or cavity. The method may further include arranging a photonic integrated circuit (PIC) die over the redistribution layer so that the photonic integrated circuit (PIC) die is on the stop-ring structure. The method may also include forming a molded package by forming a mold structure to at least partially cover the photonic integrated circuit (PIC) die to form the photonic integrated circuit package.

公开(公告)号：US11018080B2

公开(公告)日：2021-05-25

申请号：US16087621

申请日：2017-03-17

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Roshan Weerasekera ,  Surya Bhattacharya ,  Ka Fai Chang ,  Vempati Srinivasa Rao

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: Various embodiments may provide a semiconductor package. The semiconductor package may include a routing layer including a plurality of first layer contact elements on a first side and a plurality of second layer contact elements on a second side opposite the first side, and a first semiconductor die including a plurality of first electrical die contact elements coupled to the plurality of first layer contact elements. The semiconductor package may further include a second semiconductor die including a plurality of second electrical die contact elements coupled to the plurality of second layer contact elements, and a mold structure covering the second semiconductor die. A first pitch between neighbouring first electrical die contact elements may be greater than a second pitch between neighbouring second electrical die contact elements.