公开(公告)号：US20200321926A1

公开(公告)日：2020-10-08

申请号：US16829768

申请日：2020-03-25

Applicant: ANALOG DEVICES, INC.

Inventor： Ralph D. Moore ,  Jesse Bankman

IPC: H03F3/185 ,  H03F3/45 ,  H03G3/30 ,  H03G1/00

Abstract: Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

公开(公告)号：US11658621B2

公开(公告)日：2023-05-23

申请号：US16829768

申请日：2020-03-25

Applicant: ANALOG DEVICES, INC.

Inventor： Ralph D. Moore ,  Jesse Bankman

IPC: H03F3/45 ,  H03F3/185 ,  H03G3/30 ,  H03G1/00

CPC classification number: H03F3/185 ,  H03F3/45183 ,  H03F3/45201 ,  H03G1/0088 ,  H03G3/301 ,  H03F2203/45288 ,  H03F2203/45488 ,  H03F2203/45506

Abstract: Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

公开(公告)号：US10608600B2

公开(公告)日：2020-03-31

申请号：US15205973

申请日：2016-07-08

Applicant: ANALOG DEVICES, INC.

Inventor： Ralph D. Moore ,  Jesse Bankman

IPC: H03F1/14 ,  H03F3/185 ,  H03F3/45 ,  H03G3/30 ,  H03G1/00

Abstract: Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

公开(公告)号：US20250167793A1

公开(公告)日：2025-05-22

申请号：US18933599

申请日：2024-10-31

Applicant: Analog Devices, Inc.

Inventor： Nicholas S. Zakas ,  Huseyin Dinc ,  Jesse Bankman

IPC: H03M1/10

Abstract: An analog-to-digital converter (ADC) system for switching between a first operating mode and a second operating mode, where both the first operating mode and the second operating mode can include post-calibration analog-to-digital conversions, where a hardware circuitry configuration of the second operating mode can differ from a hardware circuitry configuration of the first operating mode, can include hardware circuitry. The ADC system can also include a controller, which can be configured to control the hardware circuitry to control switching between the first operating mode and the second operating mode in response to a command to switch from the first operating mode to the second operating mode. This can include to transmit second mode configuration information and second mode calibration information to the hardware circuitry, where the second mode configuration information can include values to configure the hardware circuitry to operate in the second operating mode and the second mode calibration information can include values to calibrate the ADC system while operating in the second operating mode.

公开(公告)号：US20150288545A1

公开(公告)日：2015-10-08

申请号：US14552296

申请日：2014-11-24

Applicant: ANALOG DEVICES, INC.

Inventor： Robert Schell ,  Jesse Bankman

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03012 ,  H04L25/03885

Abstract: Apparatus and methods for continuous-time equalization are provided. In one aspect, an apparatus includes an integrator configured to track and process an asynchronous input signal according to actual or approximated frequency-dependent subtraction. The apparatus further includes a comparator or subtractor configured to compare a threshold, output by the integrator, with the asynchronous input signal. In various embodiments, the integrator can include a leaky integrator configured to apply a transform in the form 1/(1+s/γ), wherein s can be adjusted based on the complex angular frequency of the asynchronous input signal. In various embodiments, the integrator can include a programmable network having a resistance R and a capacitance C, and γ can include 1/(RC). In various embodiments, the integrator can include one or more programmable current sources configured to adjust a level of boost in said frequency-dependent subtraction.

Abstract translation: 提供了连续时间均衡的装置和方法。 一方面，一种装置包括积分器，其被配置为根据实际或近似的频率相关减法跟踪和处理异步输入信号。 该装置还包括比较器或减法器，其被配置为将由积分器输出的阈值与异步输入信号进行比较。 在各种实施例中，积分器可以包括被配置为以1 /（1 + s /γ）形式应用变换的泄漏积分器，其中可以基于异步输入信号的复角频率来调整s。 在各种实施例中，积分器可以包括具有电阻R和电容C的可编程网络，并且γ可以包括1 /（RC）。 在各种实施例中，积分器可以包括一个或多个可编程电流源，其配置成在所述频率相关减法中调整升压电平。

公开(公告)号：US20170187339A1

公开(公告)日：2017-06-29

申请号：US15205973

申请日：2016-07-08

Applicant: ANALOG DEVICES, INC.

Inventor： Ralph D. Moore ,  Jesse Bankman

IPC: H03F3/185 ,  H03G3/30 ,  H03F3/45

Abstract: Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.