公开(公告)号：US20240079273A1

公开(公告)日：2024-03-07

申请号：US18389517

申请日：2023-11-14

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  ZAVIER ZAI YEONG TAN ,  KARTHIK BALAKRISHNAN ,  JAMES S. PAPANU ,  WEI-SHENG LEI

IPC: H01L21/78 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/02071

Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.

公开(公告)号：US20180226355A1

公开(公告)日：2018-08-09

申请号：US15945966

申请日：2018-04-05

Applicant: APPLIED MATERIALS, INC.

Inventor： JUNGRAE PARK ,  WEI-SHENG LEI ,  BRAD EATON ,  JAMES S. PAPANU ,  AJAY KUMAR

IPC: H01L23/544 ,  A47G19/22 ,  B65D47/32 ,  B65D47/24 ,  B23K26/0622 ,  H01L21/78 ,  B23K10/00

CPC classification number: H01L23/544 ,  A47G19/22 ,  A47G19/2272 ,  B23K10/003 ,  B23K26/0624 ,  B65D47/244 ,  B65D47/32 ,  H01L21/78 ,  H01L2223/5446

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.