公开(公告)号：US20040012041A1

公开(公告)日：2004-01-22

申请号：US10280492

申请日：2002-10-25

Applicant: Applied Materials, Inc.

Inventor： Lawrence C. West ,  Claes Bjorkman ,  Dan Maydan ,  Samuel Broydo

IPC: H01L021/00

CPC classification number: G02B6/43 ,  G02B6/12 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/4201 ,  G02B6/4214 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/4283

Abstract: An optical ready substrate made at least in part of a first semiconductor material and having a front side and a backside, the front side having a top surface that is of sufficient quality to permit microelectronic circuitry to be fabricated thereon using semiconductor fabrication processing techniques. The optical ready substrate includes an optical signal distribution circuit fabricated on the front side of the substrate in a first layer region beneath the top surface of the substrate. The optical signal distribution circuit is made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuitry to be fabricated thereon.

Abstract translation: 至少部分由第一半导体材料制成并且具有前侧和后侧的光学就绪衬底，所述前侧具有足够质量的顶表面，以允许使用半导体制造处理技术在其上制造微电子电路。 光学就绪衬底包括在衬底的顶表面下方的第一层区域中制造在衬底的前侧上的光信号分配电路。 光信号分配电路由互连的半导体光子元件组成，并被设计成向要在其上制造的微电子电路提供信号。

公开(公告)号：US20040114853A1

公开(公告)日：2004-06-17

申请号：US10623666

申请日：2003-07-21

Applicant: APPLIED MATERIALS, INC.

Inventor： Claes Bjorkman ,  Lawrence C. West ,  Dan Maydan ,  Samuel Broydo

IPC: G02B006/12

CPC classification number: G02B6/43 ,  G02B6/12 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/4204 ,  G02B6/4214 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/4283 ,  H01L21/84 ,  H01L27/1203

Abstract: An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.

Abstract translation: 一种制造方法，包括由第一半导体层制成的光学就绪衬底，在第一半导体层的顶部上的绝缘层和在绝缘层的顶部上的第二半导体层，其中第二半导体层具有顶表面和 横向分为包括第一区域和第二区域的两个区域，第一区域的顶表面具有足以允许在其中形成微电子电路的质量，并且第二区域包括其中形成的光信号分配电路， 所述光信号分配电路由互连的半导体光子元件组成并且被设计成向要在第二半导体层的第一区域中制造的微电子电路提供信号。

公开(公告)号：US20040013338A1

公开(公告)日：2004-01-22

申请号：US10280505

申请日：2002-10-25

Applicant: Applied Materials, Inc.

Inventor： Claes Bjorkman ,  Lawrence C. West ,  Dan Maydan ,  Samuel Broydo

IPC: G02B006/12

CPC classification number: G02B6/12004 ,  G02B6/12 ,  G02B6/30 ,  G02B6/4214 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4274 ,  G02B6/4283 ,  G02B6/43

Abstract: An article of manufacture comprising an optical ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.

Abstract translation: 一种制品，包括由第一半导体层制成的光学就绪衬底，在第一半导体层的顶部上的绝缘层和在绝缘层的顶部上的第二半导体层，其中第二半导体层具有顶表面，并且是 横向分为包括第一区域和第二区域的两个区域，第一区域的顶表面的质量足以允许在其中形成微电子电路，并且第二区域包括其中形成的光信号分配电路， 光信号分配电路由互连的半导体光子元件组成，并被设计为向要在第二半导体层的第一区域中制造的微电子电路提供信号。

公开(公告)号：US20020048929A1

公开(公告)日：2002-04-25

申请号：US09874874

申请日：2001-06-05

Applicant: Applied Materials, Inc.

Inventor： Mehul Naik ,  Samuel Broydo

IPC: H01L021/4763

CPC classification number: H01L21/76808

Abstract: A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

Abstract translation: 双镶嵌技术，在一个步骤中形成完整的通孔。 具体地，该方法将第一绝缘体层沉积在衬底上，在第一绝缘体层上方的蚀刻停止层以及蚀刻停止层顶部的第二绝缘体层。 然后通过施加根据最终通孔或通孔的尺寸的位置显影和图案化的光致抗蚀剂形成通孔掩模。 此后，可以在单个步骤中，例如使用反应离子蚀刻来蚀刻第一绝缘体层，蚀刻停止层和第二绝缘体层。 通过这三层形成的孔具有最终通孔的直径。 此后，将沟槽掩模并蚀刻到第二绝缘体层中。 沟槽蚀刻被蚀刻停止层停止。 通孔和沟槽被金属化以形成互连结构。 可以重复该技术以创建多级互连结构。