公开(公告)号：US11264460B2

公开(公告)日：2022-03-01

申请号：US16519246

申请日：2019-07-23

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Sanjeev Manhas ,  Mahendra Pakala ,  Ellie Y. Yieh

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/04 ,  H01L27/11556 ,  H01L27/11582

Abstract: The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.

公开(公告)号：US11456301B2

公开(公告)日：2022-09-27

申请号：US16931154

申请日：2020-07-16

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Sanjeev Manhas ,  Satendra Kumar Gautam

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49

Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.

公开(公告)号：US20240355929A1

公开(公告)日：2024-10-24

申请号：US18634109

申请日：2024-04-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Sanjeev Manhas ,  Imtiyaz Ahmad Khan

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H10B12/00

CPC classification number: H01L29/78645 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/315 ,  H10B12/485

Abstract: A memory device including at least one transistor having a dual gate structure comprising a first gate metal and a second gate metal, wherein the first gate metal has a work function of less than 4.55 eV and the second gate metal has a work function greater than 4.55 eV. A method of forming the memory device is also provided.

公开(公告)号：US10727232B2

公开(公告)日：2020-07-28

申请号：US16243551

申请日：2019-01-09

Applicant: Applied Materials, Inc.

Inventor： Arvind Kumar ,  Mahendra Pakala ,  Sanjeev Manhas ,  Satendra Kumar Gautam

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49

Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.