公开(公告)号：US20140273354A1

公开(公告)日：2014-09-18

申请号：US13841418

申请日：2013-03-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Sesh RAMASWAMI ,  Chin Hock TOH ,  Niranjan KUMAR

IPC: H01L21/52 ,  H01L21/302

CPC classification number: H01L21/52 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/81

Abstract: A method of fabricating a 3D chip stack uses an interposer and an electronic circuit substrate comprising a plurality of electronic circuits. The electrical contacts of the electronic circuit substrate are bonded and electrically coupled to bumps of the interposer. A molding compound is applied over the electronic circuits to form a molded structure. The molded structure is thinned to have a second molded thickness that is less than the first molded thickness, and the interposer is thinned to a second interposer thickness that is less than a first interposer thickness.

Abstract translation: 制造3D芯片堆叠的方法使用包括多个电子电路的插入件和电子电路基板。 电子电路基板的电触点被接合并电耦合到插入器的凸块。 在电子电路上施加模塑料以形成模制结构。 将模制结构变薄以具有小于第一模制厚度的第二模制厚度，并且将插入件变薄到小于第一插入件厚度的第二插入件厚度。