公开(公告)号：US09047092B2

公开(公告)日：2015-06-02

申请号：US13724094

申请日：2012-12-21

申请人： ARM LIMITED

发明人： Mélanie Emanuelle Lucie Teyssier ,  Philippe Pierre Maurice Luc ,  Albin Pierick Tonnerre

IPC分类号： G06F9/38

CPC分类号： G06F9/38 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3855 ,  G06F2212/25

摘要： A load store pipeline 18 includes an issue queue 20 and load store circuitry 24. The load store circuitry 24 includes the plurality of access slot circuits 26 to 40. Dependency tracking circuitry 42, 44, 46, 48 serves to track a freeable number of access slot circuits 26 to 42 corresponding to the sum of access slot circuits that are empty and those processing data access instructions which have not bypassed any preceding data access instructions within the program execution order.

摘要翻译： 加载存储流水线18包括发布队列20和加载存储电路24.加载存储电路24包括多个访问时隙电路26至40.依赖性跟踪电路42,44,46,48用于跟踪可访问数量的访问 时隙电路26至42对应于空闲的接入时隙电路之和，以及处理数据访问指令，这些处理数据访问指令在程序执行顺序中没有绕过任何先前的数据访问指令。

公开(公告)号：US09424045B2

公开(公告)日：2016-08-23

申请号：US13752621

申请日：2013-01-29

申请人： ARM LIMITED

发明人： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon ,  Frederic Claude Marie Piry ,  Albin Pierick Tonnerre

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/30014 ,  G06F9/30196

摘要： An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

摘要翻译： 一种装置和方法包括执行电路，其包括宽操作数执行单元，其被配置为允许在单个指令的执行期间处理最多N位的操作数数据。 解码器电路针对每个指令对至少一个控制数据块进行解码并生成至少一个控制数据块，该控制数据块标识由执行电路执行的操作和用于该指令的至少两个可重新组合的控制数据块。 发出队列控制电路然后为发送队列中的每个至少两个数据块和相关操作数数据的高达M位分配一个时隙，并标记这些分配的时隙以标识它们包含可重新组合的控制数据块。 所述问题队列控制电路与包含在所述至少两个控制数据块的所分配的时隙中的操作数数据一起向所述宽操作数执行单元发出组合块。

公开(公告)号：US09361112B2

公开(公告)日：2016-06-07

申请号：US13865371

申请日：2013-04-18

申请人： ARM Limited

发明人： Clément Marc Demongeot ,  Louis-Marie Vincent Mouton ,  Frédéric Claude Marie Piry ,  Jocelyn Francois Orion Jaubert ,  Albin Pierick Tonnerre

IPC分类号： G06F9/30 ,  G06F7/38 ,  G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/3806

摘要： A data processing apparatus executes call instructions, and after a sequence of instructions executed in response to a call instruction a return instruction causes the program flow to return to a point in the program sequence associated with that call instruction. The data processing apparatus is configured to speculatively execute instructions in dependence on a predicted outcome of earlier instructions and a return address prediction unit is configured to store return addresses associated with unresolved call instructions. The return address prediction unit comprises: a stack portion onto which return addresses associated with unresolved call instructions are pushed, and from which a return address is popped when a return instruction is speculatively executed; and a buffer portion which stores an entry for each unresolved call instruction executed and for each return instruction which is speculatively executed.

摘要翻译： 数据处理装置执行呼叫指令，并且在响应于呼叫指令执行的指令序列之后，返回指令使程序流程返回到与该呼叫指令相关联的程序序列中的一个点。 数据处理装置被配置为根据早期指令的预测结果推测执行指令，并且返回地址预测单元被配置为存储与未解决的呼叫指令相关联的返回地址。 返回地址预测单元包括：堆栈部分，在其上推送与未解决的呼叫指令相关联的返回地址，并且当推测性地执行返回指令时从该地址弹出返回地址; 以及缓冲部分，其存储针对执行的每个未解决的调用指令的条目和针对被推测执行的每个返回指令。

公开(公告)号：US09223701B2

公开(公告)日：2015-12-29

申请号：US13861622

申请日：2013-04-12

申请人： ARM LIMITED

发明人： Frederic Claude Marie Piry ,  Philippe Jean-Pierre Raphalen ,  Melanie Emanuelle Lucie Teyssier ,  Albin Pierick Tonnerre

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0831 ,  G06F9/30 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815

摘要： A data processing apparatus is provided in which a processor unit accesses data values stored in a memory and a cache stores local copies of a subset of the data values. The cache maintains a status value for each local copy stored in the cache. When the processor unit executes a load-exclusive operation, a first data value is loaded from a specified memory location and an exclusive use monitor begins monitoring the specified memory location for accesses. When the processor unit executes a store-exclusive operation, a second data value is stored to the specified memory location if the exclusive use monitor indicates that the first data value has not been modified since the load-exclusive operation was executed. When a local copy of the first data value is stored in the cache and the status value for the local copy of the first data value indicates that the processor unit has exclusive usage of the first data value, the data processing apparatus is configured to prevent modification of the status value for a predetermined time period after the processor unit has executed the load-exclusive operation.

摘要翻译： 提供了一种数据处理装置，其中处理器单元访问存储在存储器中的数据值，并且高速缓存存储数据值的子集的本地副本。 高速缓存为存储在缓存中的每个本地副本维护一个状态值。 当处理器单元执行负载专用操作时，从指定的存储器位置加载第一数据值，并且专用监视器开始监视指定的存储器位置以进行访问。 当处理器单元执行存储专用操作时，如果独占使用监视器指示执行了负载独占操作后第一数据值未被修改，则将第二数据值存储到指定的存储器位置。 当第一数据值的本地副本存储在高速缓存中时，第一数据值的本地副本的状态值指示处理器单元具有第一数据值的独占使用时，数据处理装置被配置为防止修改 在处理器单元执行负载独占操作之后的预定时间段内的状态值。

公开(公告)号：US20140181416A1

公开(公告)日：2014-06-26

申请号：US13724094

申请日：2012-12-21

申请人： ARM LIMITED

发明人： Mélanie Emanuelle Lucie Teyssier ,  Philippe Pierre Maurice Luc ,  Albin Pierick Tonnerre

IPC分类号： G06F12/08

CPC分类号： G06F9/38 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3855 ,  G06F2212/25

摘要： A load store pipeline 18 includes an issue queue 20 and load store circuitry 24. The load store circuitry 24 includes the plurality of access slot circuits 26 to 40. Dependency tracking circuitry 42, 44, 46, 48 serves to track a freeable number of access slot circuits 26 to 42 corresponding to the sum of access slot circuits that are empty and those processing data access instructions which have not bypassed any preceding data access instructions within the program execution order.

摘要翻译： 加载存储流水线18包括发布队列20和加载存储电路24.加载存储电路24包括多个访问时隙电路26至40.依赖性跟踪电路42,44,46,48用于跟踪可访问数量的访问 时隙电路26至42对应于空闲的接入时隙电路之和，以及处理数据访问指令，这些处理数据访问指令在程序执行顺序中没有绕过任何先前的数据访问指令。