公开(公告)号：US20150371718A1

公开(公告)日：2015-12-24

申请号：US14310162

申请日：2014-06-20

Applicant: ARM LIMITED

Inventor： Alan Jeremy BECKER ,  Chiloda Ashan Senerath PATHIRANE ,  Robert Campbell AITKEN

IPC: G11C29/14

CPC classification number: G11C29/14 ,  G06F11/008 ,  G11C29/16 ,  G11C2029/0409

Abstract: A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location. Control circuitry detects the MBIST request and reserves for testing at least one reserved memory location including the target memory location. During the test procedure, the memory continues servicing memory transactions issued by the processing circuitry that target a memory location other than the reserved location reserved by the control circuitry. The processing circuitry is stalled if it attempts to access a reserved memory location. Testing consists of short bursts of transactions which occur infrequently. In this way, MBIST testing may continue while the processor is operation in the field with reduced performance impact.

Abstract translation: 数据处理装置具有至少一个存储器和处理电路。 存储器内置自检（MBIST）接口接收MBIST请求，指示要执行测试程序来测试至少一个目标存储器位置。 控制电路检测MBIST请求并保留用于测试至少一个保留的存储器位置，包括目标存储器位置。 在测试过程期间，存储器继续服务处理电路所发出的存储器事务，该处理电路针对存储器位置而不是由控制电路保留的保留位置。 如果处理电路尝试访问保留的存储器位置，则停止处理。 测试包括不经常发生的短突发事件。 这样，当处理器在现场运行时，MBIST测试可能会持续下去，从而降低性能影响。

公开(公告)号：US20150363293A1

公开(公告)日：2015-12-17

申请号：US14685799

申请日：2015-04-14

Applicant: ARM LIMITED

Inventor： Chiloda Ashan Senerath PATHIRANE ,  Allan John SKILLMAN

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3648 ,  G06F11/3664

Abstract: A target apparatus 2 for debug includes a processing pipeline 18 for executing a sequence of program instructions. A debug interface 26 receives debug command signals corresponding directly or indirectly to debug program instructions to be executed. An instruction buffer 24 stores both the debug program instructions and non-debug program instructions. An arbiter 30 selects between both the debug program instructions and the non-debug program instructions stored within the instruction buffer to form the sequence of program instructions to be executed by the processing pipeline. A complex coherent memory system 4, 6, 8, 10, 12, 14, 32 is shared by the debug program instructions and the non-debug program instructions such that they obtain the same coherent view of memory.

Abstract translation: 用于调试的目标装置2包括用于执行程序指令序列的处理流水线18。 调试接口26接收直接或间接对应于要执行的调试程序指令的调试命令信号。 指令缓冲器24存储调试程序指令和非调试程序指令。 仲裁器30在调试程序指令和存储在指令缓冲器内的非调试程序指令之间进行选择，以形成由处理管线执行的程序指令序列。 复杂的相干存储器系统4,6,8,10,12,14和32由调试程序指令和非调试程序指令共享，使得它们获得相同的存储器的相干视图。

公开(公告)号：US20150355962A1

公开(公告)日：2015-12-10

申请号：US14685779

申请日：2015-04-14

Applicant: ARM LIMITED

Inventor： Chiloda Ashan Senerath PATHIRANE ,  Allan John SKILLMAN

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/0784 ,  G06F11/079 ,  G06F11/08 ,  G06F11/1016 ,  G06F11/1044

Abstract: A data processing apparatus 2 includes error detection and correction circuitry 8 with an associated hard-error memory buffer 10. When a correctable hard-error is detected associated with a memory access to a memory 6, if the hard-error memory buffer 10 is already full, then this correctable hard-error is escalated to be handled as an uncorrectable hard-error. The escalated uncorrectable hard-error is then handled by uncorrectable error handling circuitry 14 (fatal error circuitry) which may trigger an abort of corresponding processing operations by a processor core 4 and force the relinquishing of resources within other circuit elements such as a store buffer 16.

Abstract translation: 数据处理装置2包括具有相关联的硬错误存储器缓冲器10的错误检测和校正电路8.当检测到与存储器6的存储器访问相关联的可校正硬错误时，如果硬错误存储器缓冲器10已经 完整的，那么这个可纠正的硬错误被升级为作为不可纠正的硬错误来处理。 升级的不可校正硬错误然后由不可校正的错误处理电路14（致命错误电路）处理，该电路可能触发处理器核心4中止对应的处理操作，并强制放弃其他电路元件（如存储缓冲器16）中的资源 。

公开(公告)号：US20170123808A1

公开(公告)日：2017-05-04

申请号：US14929904

申请日：2015-11-02

Applicant: ARM Limited

Inventor： Ian Michael CAULFIELD ,  Chiloda Ashan Senerath PATHIRANE

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus includes a processing pipeline comprising a plurality of stages, the plurality of stages including at least one instruction fusing stage to detect whether a block of instructions to be processed comprises a fusible group of instructions, and to generate a fused instruction to be processed by a subsequent stage of the processing pipeline when said block of instructions comprises said fusible group. However, when said block of instructions comprises a partial subset of said fusible group of instructions, the instruction fusing stage is configured to delay handling of said partial subset of said fusible group of instructions until the instruction fusing stage has determined whether at least one subsequent block of instructions to be processed comprises a remaining subset of instructions of said fusible group.

公开(公告)号：US20150363321A1

公开(公告)日：2015-12-17

申请号：US14709784

申请日：2015-05-12

Applicant: ARM LIMITED

Inventor： Allan John SKILLMAN ,  Chiloda Ashan Senerath PATHIRANE

IPC: G06F12/08

CPC classification number: G06F12/0884 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/121 ,  G06F2212/1028 ,  G06F2212/604 ,  Y02D10/13

Abstract: A data processing apparatus 2 includes a cache memory supporting parallel data loads involving both a first address and a second address. The first address is compared with TAG values stored within a first value store 10 and the second address is compared in parallel with TAG values stored within a second value store 14. The second value store 14 contains a proper subset of the data value stored within the first value store 10.

Abstract translation: 数据处理装置2包括支持涉及第一地址和第二地址两者的并行数据负载的高速缓冲存储器。 将第一地址与存储在第一值存储10中的TAG值进行比较，并且将第二地址与存储在第二值存储器14中的TAG值并行地进行比较。第二值存储器14包含存储在第二值存储器10内的数据值的适当子集。 第一商店10。

公开(公告)号：US20140122846A1

公开(公告)日：2014-05-01

申请号：US13664659

申请日：2012-10-31

Applicant: ARM LIMITED

Inventor： Vladimir VASEKIN ,  Allan John SKILLMAN ,  Chiloda Ashan Senerath PATHIRANE ,  Jean-Baptiste BRELOT

IPC: G06F9/38

CPC classification number: G06F9/3806

Abstract: An integrated circuit 2 incorporates prefetch circuitry 12 for prefetching program instructions from a memory 6. The prefetch circuitry 12 includes a branch target address cache 28. The branch target address cache 28 stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory 6. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry 32 which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned.

Abstract translation: 集成电路2包含用于从存储器6预取程序指令的预取电路12.预取电路12包括分支目标地址高速缓存28.分支目标地址高速缓存28存储指示从先前遇到的分支指令的分支目标地址 对于每个先前遇到的分支指令，分支目标地址高速缓存存储指示先前遇到的分支指令的获取地址的标签值。 存储的标签值由标签值生成电路32产生，标签值生成电路32对获取地址的一部分执行散列函数，使得标签值的位长度小于相关提取地址的位长度。