公开(公告)号：US10592146B2

公开(公告)日：2020-03-17

申请号：US15635099

申请日：2017-06-27

Applicant: ARM Limited

Inventor： Sharjeel Saeed ,  Kushan Vijaykumar Vyas ,  Michal Karol Bogusz ,  Piotr Tadeusz Chrobak ,  Ozgur Ozkurt

IPC: G06F13/00 ,  G06F3/06 ,  G09G5/395 ,  G06F13/38

Abstract: A method of operating a data processing system 4 is disclosed that comprises producing data in the form of blocks of data, where each block of data represents a particular region of a data array, processing the data using a processing operation in which one or more output data values are each determined using data values from plural different lines of the data array, storing the processed data in a memory 21 of the data processing system, and reading the data from the memory 21 in the form of lines.

公开(公告)号：US10210595B2

公开(公告)日：2019-02-19

申请号：US15438663

申请日：2017-02-21

Applicant: ARM Limited

Inventor： Sharjeel Saeed ,  Daren Croxford ,  Kushan Vijaykumar Vyas

IPC: G06T1/60 ,  G09G5/36 ,  G09G5/00 ,  G06T1/20 ,  G06T3/60 ,  G09G3/36

Abstract: A method of operating a data processing system 4 comprises a first processing stage 11, 12 of the data processing system producing data according to a first pattern, and a second processing stage 20 of the data processing system using the data produced by the first processing stage 11, 12 according to a second different pattern. The data processing system 4 deactivates the first processing stage 11, 12 when the first processing stage 11, 12 has produced a set of data that includes sufficient data to allow the set of data to be used by the second processing stage 20 according to the second pattern, and re-activates the first processing stage 11, 12 based on the use of that set of data by the second processing stage 20.

公开(公告)号：US20170256027A1

公开(公告)日：2017-09-07

申请号：US15438663

申请日：2017-02-21

Applicant: ARM Limited

Inventor： Sharjeel Saeed ,  Daren Croxford ,  Kushan Vijaykumar Vyas

IPC: G06T1/60 ,  G06T1/20 ,  G06T3/60

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T3/60 ,  G09G3/3611 ,  G09G5/00 ,  G09G5/363

Abstract: A method of operating a data processing system 4 comprises a first processing stage 11, 12 of the data processing system producing data according to a first pattern, and a second processing stage 20 of the data processing system using the data produced by the first processing stage 11, 12 according to a second different pattern. The data processing system 4 deactivates the first processing stage 11, 12 when the first processing stage 11, 12 has produced a set of data that includes sufficient data to allow the set of data to be used by the second processing stage 20 according to the second pattern, and re-activates the first processing stage 11, 12 based on the use of that set of data by the second processing stage 20.

公开(公告)号：US20180373432A1

公开(公告)日：2018-12-27

申请号：US15635099

申请日：2017-06-27

Applicant: ARM Limited

Inventor： Sharjeel Saeed ,  Kushan Vijaykumar Vyas ,  Michal Karol Bogusz ,  Piotr Tadeusz Chrobak ,  Ozgur Ozkurt

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0673 ,  G06F13/38 ,  G09G5/395 ,  G09G2330/021

Abstract: A method of operating a data processing system 4 is disclosed that comprises producing data in the form of blocks of data, where each block of data represents a particular region of a data array, processing the data using a processing operation in which one or more output data values are each determined using data values from plural different lines of the data array, storing the processed data in a memory 21 of the data processing system, and reading the data from the memory 21 in the form of lines.

公开(公告)号：US09805478B2

公开(公告)日：2017-10-31

申请号：US15067683

申请日：2016-03-11

Applicant: ARM LIMITED

Inventor： Daren Croxford ,  Sharjeel Saeed ,  Kushan Vijaykumar Vyas

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T11/60 ,  G06T15/00

CPC classification number: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T11/60 ,  G06T15/005 ,  G06T2210/32 ,  G06T2210/62

Abstract: Apparatus and a corresponding method for processing image data are provided. The apparatus has compositing circuitry to generate a composite layer for a frame for display from image data representing plural layers of content within the frame. Plural latency buffers are provided to store at least a portion of the image data representing the plural layers. At least one of the plural latency buffers is larger than at least one other of the plural latency buffers. The compositing circuitry is responsive to at least one characteristic of the plural layers of content to allocate the plural layers to respective latency buffers of the plural latency buffers. Image data information for a layer allocated to the larger latency buffer is available for analysis earlier than that of the layers allocated to the smaller latency buffers and processing efficiencies can then result.