中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

33 records (took 0.018 seconds)

    Data processing system and method
    1.
    发明授权
    Data processing system and method 有权

    公开(公告)号：US11824977B2

    公开(公告)日：2023-11-21

    申请号：US16940770

    申请日：2020-07-28

    Applicant: Arm Limited

    Inventor： Sharjeel Saeed ,  Daren Croxford ,  Dominic Hugo Symes

    IPC: H04L9/08 ,  G06N3/045 ,  G06N3/08 ,  H04L9/32

    CPC classification number: H04L9/0861 ,  G06N3/045 ,  G06N3/08 ,  H04L9/3247

    Abstract: A data processing system including storage. The data processing system also includes at least one processor to generate output data using at least a portion of a first neural network layer and generate a key associated with at least the portion of the first neural network layer. The at least one processor is further operable to obtain the key from the storage and obtain a version of the output data for input into a second neural network layer. Using the key, the at least one processor is further operable to determine whether the version of the output data differs from the output data.

    GRAPHICS PROCESSING
    3.
    发明申请
    GRAPHICS PROCESSING 有权

    公开(公告)号：US20230126531A1

    公开(公告)日：2023-04-27

    申请号：US17512425

    申请日：2021-10-27

    Applicant: Arm Limited

    Inventor： Daren Croxford ,  Mathieu Jean Joseph Robart ,  Sharjeel Saeed

    IPC: G06T15/06 ,  G06T15/08 ,  G06T17/10 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60

    Abstract: In a graphics processing system comprising a graphics processor, a main memory, and a memory management unit, when rendering a frame that represents a view of a scene comprising one or more objects using a ray tracing process and the ray tracing process requires a traversal of a ray tracing acceleration data structure indicative of the distribution of geometry for the scene being rendered to determine geometry for the scene that may be intersected by a ray, at least part of the traversal of the ray tracing acceleration data structure is performed by the memory management unit (MMU).

    DATA PROCESSING SYSTEMS
    4.
    发明申请
    DATA PROCESSING SYSTEMS 审中-公开

    公开(公告)号：US20190005924A1

    公开(公告)日：2019-01-03

    申请号：US15640780

    申请日：2017-07-03

    Applicant: ARM Limited

    Inventor： Sharjeel Saeed ,  Jayavarapu Srinivasa Rao ,  Ozgur Ozkurt ,  Daren Croxford

    IPC: G09G5/395 ,  G09G5/393 ,  G09G5/36

    Abstract: A method of operating a data processing system is disclosed for a data processing system that comprises a display and a display controller. The method comprises the display controller providing to the display data for an output surface to be displayed, storing the data in a memory of the display, and the display reading the data from the memory and displaying the output surface. The method further comprises the display controller indicating to the display a particular memory address of the memory, and the display using the indication to control the reading of data from the memory. The display controller may provide to the display image data for one or more sub-regions of the output surface that were not present in a previous version of the output surface.

    Managing memory access for convolutional neural networks
    5.
    发明授权
    Managing memory access for convolutional neural networks 有权

    公开(公告)号：US10977184B2

    公开(公告)日：2021-04-13

    申请号：US16447728

    申请日：2019-06-20

    Applicant: Apical Limited ,  Arm Limited

    Inventor： Sharjeel Saeed ,  Daren Croxford ,  Graeme Leslie Ingram

    IPC: G06F12/00 ,  G06F12/10 ,  G06N3/04

    Abstract: A method for managing memory access for implementing at least one layer of a convolutional neural network is provided. The method comprises predicting an access procedure in relation to a portion of memory based on a characteristic of the convolutional neural network. In response to the prediction, the method comprises performing an operation to obtain and store a memory address translation, corresponding to the portion of memory, in storage in advance of the predicted access procedure. An apparatus is provided comprising at least one processor and storage. The apparatus is configured to predict an access procedure in relation to a portion of memory which is external to the processor. In response to the prediction, the apparatus is configured to obtain and store a memory address translation corresponding to the portion of memory in storage in advance of the predicted access procedure.

    Data processing systems
    6.
    发明授权
    Data processing systems 有权

    公开(公告)号：US10216412B2

    公开(公告)日：2019-02-26

    申请号：US15432769

    申请日：2017-02-14

    Applicant: ARM Limited

    Inventor： Sharjeel Saeed

    IPC: G06F13/00 ,  G06F3/06

    Abstract: Operating a data processing system including producing data in the form of plural blocks of data, where each block of data represents a particular region of an output data array, storing the data in a memory of the data processing system, and reading the data from the memory in the form of lines. Storing the data in the memory comprises storing each block of data of a first row of blocks of data in the memory at one or more memory addresses of a first set of memory addresses of a sequence of memory addresses for the memory, and storing each block of data of a second row of blocks of data in the memory at one or more memory addresses of a second set of different memory addresses of the sequence of memory addresses for the memory.

    Compositing plural layer of image data for display
    8.
    发明授权
    Compositing plural layer of image data for display 有权

    公开(公告)号：US09805478B2

    公开(公告)日：2017-10-31

    申请号：US15067683

    申请日：2016-03-11

    Applicant: ARM LIMITED

    Inventor： Daren Croxford ,  Sharjeel Saeed ,  Kushan Vijaykumar Vyas

    IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T11/60 ,  G06T15/00

    CPC classification number: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T11/60 ,  G06T15/005 ,  G06T2210/32 ,  G06T2210/62

    Abstract: Apparatus and a corresponding method for processing image data are provided. The apparatus has compositing circuitry to generate a composite layer for a frame for display from image data representing plural layers of content within the frame. Plural latency buffers are provided to store at least a portion of the image data representing the plural layers. At least one of the plural latency buffers is larger than at least one other of the plural latency buffers. The compositing circuitry is responsive to at least one characteristic of the plural layers of content to allocate the plural layers to respective latency buffers of the plural latency buffers. Image data information for a layer allocated to the larger latency buffer is available for analysis earlier than that of the layers allocated to the smaller latency buffers and processing efficiencies can then result.

    GRAPHICS PROCESSORS
    10.
    发明公开
    GRAPHICS PROCESSORS 审中-公开

    公开(公告)号：US20240036932A1

    公开(公告)日：2024-02-01

    申请号：US18359002

    申请日：2023-07-26

    Applicant: Arm Limited

    Inventor： Daren Croxford ,  Sharjeel Saeed ,  Isidoros Sideris

    IPC: G06F9/50 ,  G06T15/00

    CPC classification number: G06F9/505 ,  G06T15/005

    Abstract: Disclosed herein is a graphics processor that comprises a programmable execution unit operable to execute programs to perform graphics processing operations. The graphics processor further comprises a dedicated machine learning processing circuit operable to perform processing operations for machine learning processing tasks. The machine learning processing circuit is in communication with the programmable execution unit internally to the graphics processor. In this way, the graphics processor can be configured such that machine learning processing tasks can be performed by the programmable execution unit, the machine learning processing circuit, or a combination of both, with the different units being able to message each other accordingly to control the processing.

Patent Agency Ranking