公开(公告)号：US20210058237A1

公开(公告)日：2021-02-25

申请号：US16546596

申请日：2019-08-21

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Matthias Lothar BOETTCHER ,  Prakash S. RAMRAKHYANI

IPC: H04L9/06 ,  H04L9/32 ,  G06F12/14 ,  G06F21/72 ,  G06F13/16

Abstract: An apparatus and method are described, the apparatus comprising memory control circuitry configured to control access to data stored in memory, and memory security circuitry configured to generate encrypted data to be stored in the memory, the encrypted data being based on target data and a first one-time-pad (OTP). In response to an OTP update event indicating that the first OTP is to be updated to a second OTP different to the first OTP, the memory security circuitry is configured to generate a re-encryption value based on the first OTP and the second OTP, and the memory security circuitry is configured to issue a re-encryption request to cause updated encrypted data to be generated in a downstream component based on the encrypted data and the re-encryption value and to cause the encrypted data to be replaced in the memory by the updated encrypted data.

公开(公告)号：US20190155742A1

公开(公告)日：2019-05-23

申请号：US16169219

申请日：2018-10-24

Applicant: Arm Limited

Inventor： Prakash S. RAMRAKHYANI ,  Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  Stephan DIESTELHORST

IPC: G06F12/10

Abstract: There is provided an apparatus that includes an input address port to receive an input address from processor circuitry. Address storage stores a translation between the input address and an output address in an output address space. An output address port outputs the output address. An input data port receives data. Data storage stores the data. An output data port outputs the data stored in the data storage and control circuitry causes the data storage to store the translation between the input address and the output address. The control circuitry issues a signal to cause a page walk to occur in response to the input address being absent from the address storage and the data storage.

公开(公告)号：US20190155748A1

公开(公告)日：2019-05-23

申请号：US16181474

申请日：2018-11-06

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  Prakash S. RAMRAKHYANI

IPC: G06F12/1027

Abstract: Memory address translation apparatus comprises page table access circuitry to access page table data to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the virtual address space, one or more instances of the translation data; and control circuitry, responsive to an input initial memory address to be translated, to request retrieval of translation data for the input initial memory address from the translation data buffer and, before completion of processing of the request for retrieval from the translation data buffer, to initiate retrieval of translation data for the input initial memory address by the page table access circuitry.

公开(公告)号：US20190155747A1

公开(公告)日：2019-05-23

申请号：US16169206

申请日：2018-10-24

Applicant: Arm Limited

Inventor： Andreas Lars SANDBERG ,  Nikos NIKOLERIS ,  Prakash S. RAMRAKHYANI ,  Stephan DIESTELHORST

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/0808 ,  G06F12/06 ,  G06F13/16 ,  G06F3/06

Abstract: There is provided an apparatus that includes an input port to receive, from a requester, any one of: a lookup operation comprising an input address, and a maintenance operation. Maintenance queue circuitry stores a maintenance queue of at least one maintenance operation and address storage stores a translation between the input address and an output address in an output address space. In response to receiving the input address, the output address is provided in dependence on the maintenance queue. In response to storing the maintenance operation, the maintenance queue circuitry causes an acknowledgement to be sent to the requester. By providing a separate maintenance queue for performing the maintenance operation, there is no need for a requester to be blocked while maintenance is performed.

公开(公告)号：US20220114102A1

公开(公告)日：2022-04-14

申请号：US17069057

申请日：2020-10-13

Applicant: Arm Limited

Inventor： Wei WANG ,  Prakash S. RAMRAKHYANI ,  Gustavo Federico PETRI

IPC: G06F12/0875 ,  G06F12/0882 ,  G06F12/1009 ,  G06F13/16 ,  G06F9/30 ,  G06F9/38 ,  G06F11/14 ,  G06F11/20 ,  G06F11/30

Abstract: An apparatus comprises a write buffer to buffer store requests issued by the processing circuitry, prior to the store data being written to at least one cache. Draining circuitry detects a draining trigger event having potential to cause loss of state stored in the at least one cache. In response to the draining trigger event, the draining circuitry performs a draining operation to identify whether the write buffer buffers any committed store requests requiring persistence, and when the write buffer buffers at least one committed store request requiring persistence, to cause the store data associated with the at least one committed store request to be written to persistent memory. This helps to eliminate barrier instructions from software, simplifying persistent programming and improving performance.

公开(公告)号：US20200073819A1

公开(公告)日：2020-03-05

申请号：US16120637

申请日：2018-09-04

Applicant: Arm Limited

Inventor： Geoffrey Wyman BLAKE ,  Prakash S. RAMRAKHYANI ,  Andreas Lars SANDBERG

IPC: G06F12/1009 ,  G06F12/0802

Abstract: Address translation circuitry performs virtual-to-physical address translations using a page table hierarchy of page table entries, wherein a translation between a virtual address and a physical address is defined in a last level page table entry of the page table hierarchy. The address translation circuitry is responsive to receipt of the virtual address to perform a translation determination with reference to the page table hierarchy, wherein an intermediate level page table entry of the page table hierarchy stores an intermediate level pointer to the last level page table entry. The translation determination comprises: calculating a higher level pointer to the intermediate level page table entry by applying a first predetermined function to the virtual address, calculating the intermediate level pointer by applying a second predetermined function to the virtual address, and initiating a memory access to retrieve in parallel the intermediate level pointer from the intermediate level page table entry and the translation from the last level page table entry.

公开(公告)号：US20190102272A1

公开(公告)日：2019-04-04

申请号：US15724433

申请日：2017-10-04

Applicant: ARM LIMITED

Inventor： Prakash S. RAMRAKHYANI ,  Jonathan Curtis BEARD

IPC: G06F11/30

CPC classification number: G06F11/3024 ,  G06F11/3037 ,  G06F2201/885 ,  G06F2212/1024 ,  G06F12/0802 ,  G06F9/46

Abstract: An apparatus comprises a plurality of memory units organised as a hierarchical memory system, wherein each of at least some of the memory units is associated with a processor element; predictor circuitry to perform a prediction process to determine a predicted redundancy period of result data of a data processing operation to be performed, indicating a predicted point when said result data will be next accessed; and an operation controller to cause a selected processor element to perform said data processing operation, wherein said selected processor element is selected based on said predicted redundancy period.

公开(公告)号：US20220014379A1

公开(公告)日：2022-01-13

申请号：US16925723

申请日：2020-07-10

Applicant: Arm Limited

Inventor： Roberto AVANZI ,  Andreas Lars SANDBERG ,  Michael Andrew CAMPBELL ,  Matthias Lothar BOETTCHER ,  Prakash S. RAMRAKHYANI

IPC: H04L9/32 ,  G06F21/64 ,  G06F21/57 ,  H04W12/06

Abstract: Apparatuses and method are disclosed for protecting the integrity of data stored in a protected area of memory. Data in the protected area of memory is retrieved in data blocks and an authentication code is associated with a memory granule contiguously comprising a first data block and a second data block. Calculation of the authentication code comprises a cryptographic calculation based on a first hash value determined from the first data block and a second hash value determined from the second data block. A hash value cache is provided to store hash values determined from data blocks retrieved from the protected area of the memory. When the first data block and its associated authentication code are retrieved from memory, a lookup for the second hash value in the hash value cache is performed, and a verification authentication code is calculated for the memory granule to which that data block belongs. The integrity of the first data block is contingent on the verification authentication code matching the retrieved authentication code.

公开(公告)号：US20190243778A1

公开(公告)日：2019-08-08

申请号：US16342644

申请日：2017-11-29

Applicant: ARM LIMITED

Inventor： Nikos NIKOLERIS ,  Andreas Lars SANDBERG ,  Prakash S. RAMRAKHYANI ,  Stephan DIESTELHORST

IPC: G06F12/1009 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/657 ,  G11C8/06 ,  G11C11/4082 ,  G11C11/4096

Abstract: Memory address translation apparatus comprises page table access circuitry to access a page table to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the initial address space, one or more instances of the translation data; the translation data buffer comprising: an array of storage locations arranged in rows and columns; a row buffer comprising a plurality of entries each to store information from a respective portion of a row of the array; and comparison circuitry responsive to a key value dependent upon at least the initial memory address, to compare the key value with information stored in each of at least one key entry of the row buffer, each key entry having an associated value entry for storing at least a representation of a corresponding output memory address, and to identify which of the at least one key entry, if any, is a matching key entry storing information matching the key value; and output circuitry to output, when there is a matching key entry, at least the representation of the output memory address in the value entry associated with the matching key entry.

公开(公告)号：US20170024327A1

公开(公告)日：2017-01-26

申请号：US15208816

申请日：2016-07-13

Applicant: ARM Limited

Inventor： Ali SAIDI ,  Prakash S. RAMRAKHYANI

IPC: G06F12/12 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/60

Abstract: A cache memory and method of operating a cache memory are provided. The cache memory comprises cache storage that stores cache lines for a plurality of requesters and cache control circuitry that controls insertion of a cache line into the cache storage when a memory access request from one of the plurality of requesters misses in the cache memory. The cache memory further has cache occupancy estimation circuitry that holds a count of insertions of cache lines into the cache storage for each of the plurality of requesters over a defined period. The count of cache line insertions for each requester thus provides an estimation of the cache occupancy associated with each requester.

Abstract translation: 提供了高速缓存存储器和操作高速缓冲存储器的方法。 高速缓冲存储器包括缓存存储器，其存储用于多个请求者的高速缓存行和高速缓存控制电路，当来自多个请求者之一的存储器访问请求在高速缓冲存储器中丢失时，高速缓存控制电路控制高速缓存行插入到高速缓存存储器中。 高速缓存存储器还具有高速缓存占用估计电路，该电路将所述多个请求者中的每一个的高速缓存行的高速缓存行的插入数保持在规定的时间段内。 因此，每个请求者的高速缓存行插入的计数提供了与每个请求者相关联的高速缓存占用的估计。