公开(公告)号：US20150154045A1

公开(公告)日：2015-06-04

申请号：US14618211

申请日：2015-02-10

Applicant: ARM Limited ,  The Regents of the University of Michigan

Inventor： Geoffrey Blake ,  Trevor Nigel Mudge ,  Nathan Yong Seng Chong ,  Ronald George Dreslinski ,  Stuart David Biles ,  Emre Özer

IPC: G06F9/46 ,  G06F12/08

CPC classification number: G06F9/467 ,  G06F9/30087 ,  G06F9/466 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/621

Abstract: A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

Abstract translation: 在具有相关性控制和硬件事务存储器控制电路的多处理器系统内提供硬件事务存储器，其用于至少部分地根据冲突数据管理处理事务的调度。 冲突数据表示处理事务之前遇到的冲突。 执行调度，使得如果冲突数据指示已经运行的处理事务中的一个先前与候选处理事务冲突，则候选处理事务将不被调度。

公开(公告)号：US10162762B2

公开(公告)日：2018-12-25

申请号：US14692959

申请日：2015-04-22

Applicant: ARM LIMITED

Inventor： Geoffrey Blake ,  Ali Ghassan Saidi ,  Mitchell Hayenga

IPC: G06F12/1027

Abstract: A data processing system 4 includes a translation lookaside buffer 6 storing mapping data entries 10 indicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generator 20 coupled to the translation lookaside buffer 6 generates hint data in dependence upon the storage of mapping data entries within the translation lookaside buffer 6. The hint generator 20 tracks the loading of mapping data entries and the eviction of mapping data entries from the translation lookaside buffer 6. The hint data is supplied to a memory controller 8 which controls how data corresponding to respective different regions of physical addresses is stored within a heterogeneous memory system, e.g. the power state of different portions of the memories storing different regions, which type of memory is used to store different regions.

公开(公告)号：US09697136B2

公开(公告)日：2017-07-04

申请号：US14494000

申请日：2014-09-23

Applicant: ARM Limited

Inventor： Ali Ghassan Saidi ,  Anirruddha Nagendran Udipi ,  Matthew Lucien Evans ,  Geoffrey Blake ,  Robert Gwilym Dimond

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/654 ,  G06F2212/681

Abstract: A data processing system utilizing a descriptor ring to facilitate communication between one or more general purpose processors and one or more devices employs a system memory management unit for managing access by the devices to a main memory. The system memory management unit uses address translation data for translating memory addresses generated by the devices into addresses supplied to the main memory. Prefetching circuitry within the system memory management unit serves to detect pointers read from the descriptor ring and to prefetch address translation data into the translation lookaside buffer of the system memory management unit.