公开(公告)号：US20150256191A1

公开(公告)日：2015-09-10

申请号：US14437237

申请日：2014-08-13

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Ryuzo Yamamoto ,  Junya Nakanishi ,  Seiko Nakamoto

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/66 ,  H03M1/08

CPC classification number: H03M1/0614 ,  H03F1/3247 ,  H03M1/00 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/66 ,  H03M1/747 ,  H04B2001/7154 ,  H04L27/2647

Abstract: The present invention relates to a control method of a D/A converter, a D/A converter, a control method of an A/D converter, and an A/D converter that can suppress an existing n-th harmonic without using a large-scale circuit, such as a bootstrap. A D/A converter (10) of the present invention is a D/A converter (10) that can suppress the generation of an existing n-th harmonic (n is an integer of 2 or more) of an analog output signal. The D/A converter (10) includes a D/A conversion unit (11) that converts an input digital signal into an analog signal and a control unit (12) that arbitrarily controls the timing of the sampling phase and the integral phase of the D/A conversion unit (11). The D/A conversion unit (11) is configured to generate an arbitrary n-th harmonic and superimpose the arbitrary n-th harmonic on an analog output signal including the existing n-th harmonic.

Abstract translation: 本发明涉及D / A转换器的控制方法，D / A转换器，A / D转换器的控制方法和可以抑制现有的n次谐波而不使用大的A / D转换器 尺度电路，例如自举。 本发明的D / A转换器（10）是可以抑制模拟输出信号的现有n次谐波（n为2以上的整数）的产生的D / A转换器（10）。 D / A转换器（10）包括将输入数字信号转换为模拟信号的D / A转换单元（11）和任意控制采样相位的定时和 D / A转换单元（11）。 D / A转换单元（11）被配置为产生任意的n次谐波，并且将任意的n次谐波叠加在包括现有的n次谐波的模拟输出信号上。

公开(公告)号：US11929760B2

公开(公告)日：2024-03-12

申请号：US17752801

申请日：2022-05-24

Applicant: Asahi Kasei Microdevices Corporation

Inventor： Ryuzo Yamamoto

IPC: H03M1/66 ,  H03M1/08 ,  H03M1/74

CPC classification number: H03M1/742 ,  H03M1/08 ,  H03M1/0863

Abstract: Provided is a DA converter for outputting an analog signal according to an input digital signal, including a plurality of current output units to be input with the digital signal, which output a current according to the digital signal to a corresponding wiring, a conversion unit provided with a plurality of feedback paths respectively coupled to wirings corresponding to the current output units, and which selects at least one wiring among the wirings corresponding to the current output units and output an analog signal according to a current flowing in the selected wiring, and a first noise reduction unit provided with a plurality of first switches each of which switches whether to electrically connect to at least one wiring among the wirings corresponding to the current output units, and reduces a noise component generated in at least one of the plurality of current output units from the electrically coupled wiring.

公开(公告)号：US09246502B2

公开(公告)日：2016-01-26

申请号：US14437237

申请日：2014-08-13

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Ryuzo Yamamoto ,  Junya Nakanishi ,  Seiko Nakamoto

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/66 ,  H03M1/08 ,  H03F1/32 ,  H03M1/00 ,  H03M1/74 ,  H04B1/715 ,  H04L27/26

CPC classification number: H03M1/0614 ,  H03F1/3247 ,  H03M1/00 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/66 ,  H03M1/747 ,  H04B2001/7154 ,  H04L27/2647

Abstract: The present invention relates to a control method of a D/A converter, a D/A converter, a control method of an A/D converter, and an A/D converter that can suppress an existing n-th harmonic without using a large-scale circuit, such as a bootstrap. A D/A converter (10) of the present invention is a D/A converter (10) that can suppress the generation of an existing n-th harmonic (n is an integer of 2 or more) of an analog output signal. The D/A converter (10) includes a D/A conversion unit (11) that converts an input digital signal into an analog signal and a control unit (12) that arbitrarily controls the timing of the sampling phase and the integral phase of the D/A conversion unit (11). The D/A conversion unit (11) is configured to generate an arbitrary n-th harmonic and superimpose the arbitrary n-th harmonic on an analog output signal including the existing n-th harmonic.

Abstract translation: 本发明涉及D / A转换器的控制方法，D / A转换器，A / D转换器的控制方法和可以抑制现有的n次谐波而不使用大的A / D转换器 尺度电路，例如自举。 本发明的D / A转换器（10）是可以抑制模拟输出信号的现有n次谐波（n为2以上的整数）的产生的D / A转换器（10）。 D / A转换器（10）包括将输入数字信号转换为模拟信号的D / A转换单元（11）和任意控制采样相位的定时和 D / A转换单元（11）。 D / A转换单元（11）被配置为产生任意的n次谐波，并且将任意的n次谐波叠加在包括现有的n次谐波的模拟输出信号上。

公开(公告)号：US10666278B2

公开(公告)日：2020-05-26

申请号：US16352859

申请日：2019-03-14

Applicant: Asahi Kasei Microdevices Corporation

Inventor： Daisuke Matsuoka ,  Ryuzo Yamamoto ,  Tatsuya Chubachi

IPC: H03M1/66 ,  H03M1/08

Abstract: To reduce distortion of output analog signals generated at a current-output DA converter. A DA converter that outputs a differential analog signal corresponding to an input digital signal is provided, including: a current output unit outputting a current corresponding to the digital signal to each of first and second wires; a converting unit outputting, as positive-side and negative-side analog signals, voltage signals based on currents flowing through the first and second wires, respectively; a first noise reducing unit having: a first switch switched to be or not to be electrically connected with the first wire; and a first buffer provided between the first switch and a reference potential; and a second noise reducing unit having: a second switch switched to be or not to be electrically connected with the second wire; and a second buffer provided between the second switch and the reference potential.

公开(公告)号：US10659068B2

公开(公告)日：2020-05-19

申请号：US16231951

申请日：2018-12-25

Applicant: Asahi Kasei Microdevices Corporation

Inventor： Ryuzo Yamamoto

IPC: H03M1/06 ,  H03M1/66 ,  H03M1/10 ,  H03F3/45

Abstract: A DA converter to reduce second-order harmonic distortion more precisely with convenient configurations. A DA converter including: a DA converting unit to input reference voltage and a digital value and output an analog signal according to the digital value based on the reference voltage; and a superimposing unit to superimpose, on the reference voltage, a superimposing signal based on the analog signal that is output from the DA converting unit, and a DA converting method are provided. The DA converter may further include a setting input unit to input setting regarding at least one of a superimposing amount and a sign of an analog signal to be included in the superimposing signal. Also, an adjusting apparatus and an adjusting method to adjust the DA converter are provided.