公开(公告)号：US09246502B2

公开(公告)日：2016-01-26

申请号：US14437237

申请日：2014-08-13

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Ryuzo Yamamoto ,  Junya Nakanishi ,  Seiko Nakamoto

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/66 ,  H03M1/08 ,  H03F1/32 ,  H03M1/00 ,  H03M1/74 ,  H04B1/715 ,  H04L27/26

CPC classification number: H03M1/0614 ,  H03F1/3247 ,  H03M1/00 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/66 ,  H03M1/747 ,  H04B2001/7154 ,  H04L27/2647

Abstract: The present invention relates to a control method of a D/A converter, a D/A converter, a control method of an A/D converter, and an A/D converter that can suppress an existing n-th harmonic without using a large-scale circuit, such as a bootstrap. A D/A converter (10) of the present invention is a D/A converter (10) that can suppress the generation of an existing n-th harmonic (n is an integer of 2 or more) of an analog output signal. The D/A converter (10) includes a D/A conversion unit (11) that converts an input digital signal into an analog signal and a control unit (12) that arbitrarily controls the timing of the sampling phase and the integral phase of the D/A conversion unit (11). The D/A conversion unit (11) is configured to generate an arbitrary n-th harmonic and superimpose the arbitrary n-th harmonic on an analog output signal including the existing n-th harmonic.

Abstract translation: 本发明涉及D / A转换器的控制方法，D / A转换器，A / D转换器的控制方法和可以抑制现有的n次谐波而不使用大的A / D转换器 尺度电路，例如自举。 本发明的D / A转换器（10）是可以抑制模拟输出信号的现有n次谐波（n为2以上的整数）的产生的D / A转换器（10）。 D / A转换器（10）包括将输入数字信号转换为模拟信号的D / A转换单元（11）和任意控制采样相位的定时和 D / A转换单元（11）。 D / A转换单元（11）被配置为产生任意的n次谐波，并且将任意的n次谐波叠加在包括现有的n次谐波的模拟输出信号上。

公开(公告)号：US20140062742A1

公开(公告)日：2014-03-06

申请号：US13882323

申请日：2012-12-27

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Junya Nakanishi ,  Yutaka Nakanishi ,  Seiko Nakamoto

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/0656 ,  H03M1/12 ,  H03M1/1265 ,  H03M1/66

Abstract: An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.

Abstract translation: 一种A / D转换器，包括：采样电路，包括连续部分，采样和保持部分，用于基于从连续部分输入的模拟信号间歇地采样输入信号，以保持和传送采样信号;以及数字部分，用于输出 从采样保持部分传送的信号作为数字信号; 以及控制电路，用于提供不连续抖动的时钟信号，并将提供抖动的时钟信号提供给采样保持部。

公开(公告)号：US20140097977A1

公开(公告)日：2014-04-10

申请号：US13996140

申请日：2012-10-31

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Seiko Nakamoto ,  Junya Nakanishi

IPC: H03M1/80

CPC classification number: H03M1/806 ,  H03M1/06 ,  H03M1/804

Abstract: A digital-analog converter circuit includes sampling capacitive elements (111, 112, . . . , 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, . . . , DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, . . . , 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, . . . , 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).

Abstract translation: 数模转换器电路包括对其一端电连接到输入端（D1，D2，...，DN）并与其断开的电容元件（111,112，...，11N）进行采样，其中 数字信号经由开关单元（SWu10），运算放大器（501），能够电连接和断开采样电容元件（111,112 ...，11N）的另一端的开关（301）输入， 和运算放大器（501）的反相输入端子和设置在开关单元（SWu10）和采样电容元件（111,112 ...，11N）之间的节点之间的开关单元（SWu40）和 运算放大器（501）的输出端子，并且能够连接和断开它们。 包括在开关（301）中的MOS晶体管的导通电阻值被设置为大于包括在开关单元（SWu40）中的MOS晶体管的导通电阻值。

公开(公告)号：US20150256191A1

公开(公告)日：2015-09-10

申请号：US14437237

申请日：2014-08-13

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Ryuzo Yamamoto ,  Junya Nakanishi ,  Seiko Nakamoto

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/66 ,  H03M1/08

CPC classification number: H03M1/0614 ,  H03F1/3247 ,  H03M1/00 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/66 ,  H03M1/747 ,  H04B2001/7154 ,  H04L27/2647

Abstract: The present invention relates to a control method of a D/A converter, a D/A converter, a control method of an A/D converter, and an A/D converter that can suppress an existing n-th harmonic without using a large-scale circuit, such as a bootstrap. A D/A converter (10) of the present invention is a D/A converter (10) that can suppress the generation of an existing n-th harmonic (n is an integer of 2 or more) of an analog output signal. The D/A converter (10) includes a D/A conversion unit (11) that converts an input digital signal into an analog signal and a control unit (12) that arbitrarily controls the timing of the sampling phase and the integral phase of the D/A conversion unit (11). The D/A conversion unit (11) is configured to generate an arbitrary n-th harmonic and superimpose the arbitrary n-th harmonic on an analog output signal including the existing n-th harmonic.

Abstract translation: 本发明涉及D / A转换器的控制方法，D / A转换器，A / D转换器的控制方法和可以抑制现有的n次谐波而不使用大的A / D转换器 尺度电路，例如自举。 本发明的D / A转换器（10）是可以抑制模拟输出信号的现有n次谐波（n为2以上的整数）的产生的D / A转换器（10）。 D / A转换器（10）包括将输入数字信号转换为模拟信号的D / A转换单元（11）和任意控制采样相位的定时和 D / A转换单元（11）。 D / A转换单元（11）被配置为产生任意的n次谐波，并且将任意的n次谐波叠加在包括现有的n次谐波的模拟输出信号上。

公开(公告)号：US11329743B2

公开(公告)日：2022-05-10

申请号：US16841600

申请日：2020-04-06

Applicant: Asahi Kasei Microdevices Corporation

Inventor： Seiko Nakamoto

IPC: H04J3/02 ,  G06F3/16 ,  H03M3/00

Abstract: In a transmission system of an audio signal etc., circuit enlargement is suppressed and deterioration of transmitting signal is reduced. A transmission system including a transmitting apparatus including a first delta-sigma modulator outputting first multi-bit delta-sigma modulated signals of three or more bits and a first code modulator code-modulating first signals of two or more bits located in bit positions higher than a predetermined bit position of the first multi-bit delta-sigma modulated signals based on at least part of a second signal located in one or more bit positions not higher than the predetermined bit position and outputting a plurality of modulated signals; a transmission path transmitting the second signal and the plurality of modulated signals; and a receiving apparatus including a first demodulator demodulating the plurality of the received modulated signals based on at least part of the received second signal is provided.

公开(公告)号：US08917196B2

公开(公告)日：2014-12-23

申请号：US13882323

申请日：2012-12-27

Applicant: Asahi Kasei Microdevices Corporation

Inventor： Junya Nakanishi ,  Yutaka Nakanishi ,  Seiko Nakamoto

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/06 ,  H03M1/66

CPC classification number: H03M1/1245 ,  H03M1/0656 ,  H03M1/12 ,  H03M1/1265 ,  H03M1/66

Abstract: An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.

Abstract translation: 一种A / D转换器，包括：采样电路，包括连续部分，采样和保持部分，用于基于从连续部分输入的模拟信号间歇地采样输入信号，以保持和传送采样信号;以及数字部分，用于输出 从采样保持部分传送的信号作为数字信号; 以及控制电路，用于提供不连续抖动的时钟信号，并将提供抖动的时钟信号提供给采样保持部。

公开(公告)号：US08830100B2

公开(公告)日：2014-09-09

申请号：US13996140

申请日：2012-10-31

Applicant: Asahi Kasei Microdevices Corporation

Inventor： Seiko Nakamoto ,  Junya Nakanishi

IPC: H03M1/66 ,  H03M1/80 ,  H03M1/06

CPC classification number: H03M1/806 ,  H03M1/06 ,  H03M1/804

Abstract: A digital-analog converter circuit includes sampling capacitive elements (111, 112, . . . , 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, . . . , DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, . . . , 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, . . . , 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).

Abstract translation: 数模转换器电路包括对其一端电连接到输入端（D1，D2，...，DN）并与其断开的电容元件（111,112，...，11N）进行采样，其中 数字信号经由开关单元（SWu10），运算放大器（501），能够电连接和断开采样电容元件（111,112 ...，11N）的另一端的开关（301）输入， 和运算放大器（501）的反相输入端子和设置在开关单元（SWu10）和采样电容元件（111,112 ...，11N）之间的节点之间的开关单元（SWu40）和 运算放大器（501）的输出端子，并且能够连接和断开它们。 包括在开关（301）中的MOS晶体管的导通电阻值被设置为大于包括在开关单元（SWu40）中的MOS晶体管的导通电阻值。