公开(公告)号：US20230214346A1

公开(公告)日：2023-07-06

申请号：US17565912

申请日：2021-12-30

Applicant: ATI TECHNOLOGIES ULC

Inventor： NIPPON RAVAL ,  PHILIP NG ,  JAROSLAW MARCZEWSKI

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F2213/0026

Abstract: Allocating peripheral component interface express (PCIe) streams in a configurable multiport PCIe controller, including: detecting, by a PCIe controller, a link by a first PCIe device; and allocating, for the link between the PCIe controller and the first PCIe device, a first one or more PCIe streams from a pool of PCIe streams.

公开(公告)号：US20230229603A1

公开(公告)日：2023-07-20

申请号：US17565666

申请日：2021-12-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： PHILIP NG ,  NIPPON RAVAL ,  DAVID A. KAPLAN ,  DONALD P. MATTHEWS, JR.

IPC: G06F13/10 ,  G06F12/084 ,  G06F12/1081

CPC classification number: G06F13/102 ,  G06F12/084 ,  G06F12/1081 ,  G06F2212/603

Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.

公开(公告)号：US20230315625A1

公开(公告)日：2023-10-05

申请号：US18331754

申请日：2023-06-08

Applicant: ATI TECHNOLOGIES ULC

Inventor： NIPPON RAVAL ,  PHILIP NG ,  ROSTISLAV S. DOBRIN

IPC: G06F12/06 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F12/063 ,  G06F13/28 ,  G06F13/4221 ,  G06F2212/206

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.

公开(公告)号：US20220206942A1

公开(公告)日：2022-06-30

申请号：US17135602

申请日：2020-12-28

Applicant: ATI Technologies ULC

Inventor： NIPPON RAVAL ,  PHILIP NG ,  ROSTISLAV S. DOBRIN

IPC: G06F12/06

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.